EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 163
EP9301-CQZ
Manufacturer Part Number
EP9301-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-CQZ
Core Size
16/32-Bit
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-TQFP, 208-VQFP
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
166MHz
No. Of Timers
4
Digital Ic Case Style
TQFP
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1136
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DS785UM1
6.1 Introduction
The EP93xx processors contain two cascaded Vectored Interrupt Controllers (VIC). A
Vectored Interrupt has improved latency compared with a simple interrupt controller, since it
provides direct information about where the interrupt’s service routine is located and
eliminates levels of software arbitration.
Each individual Vectored Interrupt Controller can handle up to 32 interrupts, but there are
more than 32 interrupts in this design. Therefore two VICs are connected in a daisy-chain,
which allows the system to handle up to 64 interrupt sources.
There are up to 16 vectored interrupts and 16 non-vectored interrupts available on each VIC.
Vectored interrupts can only generate an IRQ interrupt. Non-vectored interrupts can generate
either an IRQ interrupt or a FIQ interrupts. Vectored Interrupt Requests (IRQ) provide an
address for an Interrupt Service Routine (ISR). Reading from the vector interrupt address
register, VICxVectAddr, provides the address of the ISR, and indicates to the interrupt priority
hardware that the interrupt is being serviced. Writing to the
to the interrupt priority hardware that the interrupt has been serviced, allowing lower priority
interrupts to go active.
Registers in the VIC use a bit position for each different interrupt source. The bit position is
fixed, but the handling of each interrupt is configurable by the VIC. Software can generate
software interrupts by controlling each request line.
The VIC provides a software interface to the interrupt system. Two levels of interrupts are
available:
All interrupt inputs to the VIC are presented as active-high level sensitive signals. Any
conditioning needed to achieve this is performed by the block generating the interrupt
request. In the case of external interrupts, the GPIO block takes care of the conditioning.
Note: Some GPIO signals are not configurable but are used as inputs by other functional
Note: An interrupt vector may be overwritten when two interrupts occur simultaneously. If a
• Fast Interrupt Request (FIQ) for fast, low latency interrupt handling
• Interrupt Request (IRQ) for more general interrupts
blocks. EGPIO[2:1] are routed to the DMA controller to allow for external DMA requests.
VIC2 interrupt is immediately followed by a VIC1 interrupt, the VIC1 address will
incorrectly be the default handler address for 2 HCLK cycles. To work around this
problem, first check for pending non-vectored VIC1 interrupts in the interrupt routine. If
there are none then return from interrupt. The interrupt will immediately re-occur with the
correct vector address.
Copyright 2007 Cirrus Logic
6Vectored Interrupt Controller
VICxVectAddr
register indicates
Chapter 6
6-1
6
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