EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 47
EP9301-CQZ
Manufacturer Part Number
EP9301-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-CQZ
Core Size
16/32-Bit
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-TQFP, 208-VQFP
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
166MHz
No. Of Timers
4
Digital Ic Case Style
TQFP
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1136
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
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Part Number:
EP9301-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
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DS785UM1
2.2.7 Memory and Bus Access Errors
2.2.8 Bus Arbitration
A write data bus is used to move data from the master to a slave, while a read data bus is
used to move data from a slave to the master. Every transfer consists of:
In normal operation a master is allowed to complete all the transfers in a particular burst
before the arbiter grants another master access to the bus. However, in order to avoid
excessive arbitration latencies, it is possible for the arbiter to break up a burst, and, in such
cases, the master must re-arbitrate for the bus in order to complete the remaining transfers in
the burst.
There are several possible sources of access errors:
The arbitration mechanism is used to ensure that only one master has access to the bus that
it controls at any one time. The Arbiter performs this function by observing a number of
different requests to use the bus, and then deciding which is currently the highest priority
master requesting the bus.
The arbitration scheme can be broken down into three main areas:
• An address and control cycle
• One or more cycles for the data.
• Reads to reserved or undefined register memory addresses will return indeterminate
• Access to non-existent registers or memory may result in a bus error
• Any access to the APB control register space will complete normally, as these devices
• Access to non-existent AHB or APB registers may result in a bus error, depending on the
• External memory access is controlled by the Static Memory Controller (SMC) or the
• The main AHB system bus Arbiter
• The SDRAM slave interface Arbiter
• The EBI bus Arbiter
data. Writes to reserved or undefined memory addresses are generally ignored, but this
behavior is not guaranteed. Many register addresses are not fully decoded, so aliasing
may occur. Addresses and memory ranges listed as Reserved should not be accessed;
access behavior to these regions is not defined
have no means of signaling an error
device and nature of the error. Device specific access rules are defined in the device
descriptions
Synchronous Dynamic RAM (SDRAM) controller. In general, access to non-existent
external memory will complete normally, with reads returning random false data.
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2-9
2
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