EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 555
EP9301-CQZ
Manufacturer Part Number
EP9301-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-CQZ
Core Size
16/32-Bit
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-TQFP, 208-VQFP
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
166MHz
No. Of Timers
4
Digital Ic Case Style
TQFP
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1136
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
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Part Number:
EP9301-CQZR
Manufacturer:
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Quantity:
10 000
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DS785UM1
Address:
Default:
Definition:
Bit Descriptions:
Note: This bit reflects the status associated with the last character read from the RX FIFO. It
Note: This bit reflects the status associated with the last character read from the RX FIFO. It
Note: This bit reflects the status associated with the last character read from the RX FIFO. It
changes with reads from the RX FIFO.
changes with reads from the RX FIFO.
changes with reads from the RX FIFO.
0x808C_021C - Read/Write
0x0000_0000
HDLC Status Register. The TFS and RFS bits in this register are replicas of
bits in the UART status register.
RSVD:
PLLE:
PLLCC:
LNKIDL:
CRE:
ROR:
Copyright 2007 Cirrus Logic
Reserved. Unknown During Read.
Digital PLL Error. (Read Only)
1 - A frame receive was aborted because the DPLL lost
synchronization with the carrier.
0 - DPLL has not lost carrier during frame reception.
This bit is only valid when set up to receive Manchester-
encoded synchronous HDLC.
Digital PLL Carrier Sense. (Read Only)
1 - DPLL tacked onto a carrier.
0 - DPLL does not sense a carrier.
Link Idle. (Read Only)
0 - RX data signal has changed within two bit periods
1 - RX data signal has not changed within two bit periods.
This bit is only valid when set up to receive Manchester-
encoded synchronous HDLC.
CRC Error. (Read Only)
0 - No CRC check errors encountered in incoming frame.
1 - CRC calculated on the incoming data does not match
CRC value contained within the received frame. This bit is
set with the last data in the incoming frame along with
EOF.
Receive FIFO Overrun. (Read Only)
0 - RX FIFO has not overrun.
1 - RX logic attempted to place data in the RX FIFO while
it was full. The most recently read data is the last valid
data before the overrun. The rest of the incoming frame is
dropped. EOF is also set.
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
14-33
14
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