EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 25

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

Static Memory Burst Read Cycle
DS638F2
CSn assert to Address 1 transition time
Address assert time
AD transition to CSn deassert time
AD hold from CSn deassert time
CSn to RDn delay time
CSn to DQMn assert delay time
DA setup to AD transition time
DA setup to CSn deassert time
DA hold from AD transition time
DA hold from RDn deassert time
DQMn
WAIT
Note:
WRn
CSn
RDn
AD
DA
These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
t
ADs
t
DQMd
Parameter
t
RDd
t
Figure 12. Static Memory Burst Read Cycle Timing Measurement
ADd1

Copyright 2010 Cirrus Logic (All Rights Reserved)
t
DAs1
Symbol
t
t
t
t
t
t
t
t
DQMd
t
t
ADd1
ADd2
ADd3
DAs1
DAs2
DAh1
DAh2
ADh
RDd
t
DAh1
t
ADd2
t
t
HCLK
DAs1
t
Min
HCLK
15
0
0
-
-
-
-
-
+ 12
t
DAh1
t
ADd2
Enhanced Universal Platform SOC Processor
t
t
t
HCLK
HCLK
HCLK
t
DAs1
× (WST1 + 1)
× (WST2 + 1)
× (WST1 + 2)
Typ
-
-
-
-
-
-
-
t
t
ADd3
DAh1
t
DAs2
Max
3
1
-
-
-
-
-
-
-
-
t
DAh2
EP9315
Unit
t
ADh
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25