EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 35

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

DS638F2
ADDR valid
(Note 3,3-1)
(Note 3,3-2)
(Note 3,3-3)
DD(15:0)
DD(15:0)
(Note 1)
DIORn/
DIOWn
WRITE
IORDY
IORDY
IORDY
(Note 2)
(Note 2)
Note:
READ
1. Device address consists of signals IDECS0n, IDECS1n and IDEDA (2:0)
2. Data consists of DD (15:0)
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is
to be extended is made by the host after t
are described in the following three cases:
3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2 Device negates IORDY before t
3-3 Device negates IORDY before t
and may be asserted for no more than t
before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated
and DIORn is asserted, the device shall place read data on DD (15:0) for t
t
1

Copyright 2010 Cirrus Logic (All Rights Reserved)
Figure 20. PIO Data Transfer to/from Device
A
A
, but causes IORDY to be asserted before t
. IORDY is released prior to negation and may be asserted for no more than t
A
t
A
from the assertion of DIORn or DIOWn. The assertion and negation or IORDY
C
t
before release: no wait generated.
DDV
t
2
t
C
t
B
Enhanced Universal Platform SOC Processor
t
t
3
0
t
5
t
RD
RD
A
before asserting IORDY.
. IORDY is released prior to negation
t
t
C
6
t
6z
t
9
t
4
t
2i
C
EP9315
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