Z8F0123SB005EG Zilog, Z8F0123SB005EG Datasheet - Page 117

• Manufacturer Part Number: Z8F0123SB005EG
• Description: IC ENCORE MCU FLASH 1K 8SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0123SB005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 269-3757

Table 66. UART Control 0 Register (U0CTL0)
BITS
FIELD
RESET
R/W
ADDR
PS024314-0308
UART Control 0 and Control 1 Registers
TEN
R/W
7
0
Reserved—R/W bits must be 0 during writes; 0 when read.
NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive
Data register resets this bit to 0.
0 = The current byte is not the first data byte of a new frame
1 = The current byte is the first data byte of a new frame
MPRX—Multiprocessor Receive
Returns the value of the most recent multiprocessor bit received. Reading from the UART
Receive Data register resets this bit to 0.
The UART Control 0 and Control 1 registers
properties of the UART’s transmit and receive operations. The UART Control registers
must not be written while the UART is enabled.
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is
enabled.
0 = Transmitter disabled
1 = Transmitter enabled
REN—Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled
1 = Receiver enabled
CTSE—CTS Enable
0 = The CTS signal has no effect on the transmitter
1 = The UART recognizes the CTS signal as an enable control from the transmitter
PEN—Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit.
0 = Parity is disabled
1 = The transmitter sends data with an additional parity bit and the receiver receives an
additional parity bit
REN
R/W
6
0
CTSE
R/W
5
0
PEN
R/W
4
0
F42H
PSEL
(Table 66
R/W
3
0
Universal Asynchronous Receiver/Transmitter
and
Z8 Encore! XP
SBRK
R/W
2
0
Table
Product Specification
67) configure the
STOP
R/W
1
0
®
F0823 Series
LBEN
R/W
0
0
107