ST72F361K9T6 STMicroelectronics, ST72F361K9T6 Datasheet - Page 35
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ST72F361K9T6
Manufacturer Part Number
ST72F361K9T6
Description
MCU 8BIT 60KB FLASH MEM 32-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F361K6T6.pdf
(225 pages)
Specifications of ST72F361K9T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
LINSCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST72F36X-SK/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5615
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
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Manufacturer:
STMicroelectronics
Quantity:
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ST72F361K9T6
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INTERRUPTS (Cont’d)
7.6.2 Register Description
EXTERNAL INTERRUPT CONTROL
REGISTER 0 (EICR0)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:6 = IS3[1:0] ei3 sensitivity
The interrupt sensitivity, defined using the IS3[1:0]
bits, is applied to the ei3 external interrupts:
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bits 5:4 = IS2[1:0] ei2 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the ei2 external interrupts:
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bits 3:2 = IS1[1:0] ei1 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the ei1 external interrupts:
IS31 IS30
IS21 IS20
IS11 IS10
IS31
0
0
1
1
0
0
1
1
0
0
1
1
7
IS30
0
1
0
1
0
1
0
1
0
1
0
1
IS21
External Interrupt Sensitivity
External Interrupt Sensitivity
External Interrupt Sensitivity
IS20
Falling edge & low level
Falling edge & low level
Falling edge & low level
Rising and falling edge
Rising and falling edge
Rising and falling edge
Falling edge only
Falling edge only
Falling edge only
Rising edge only
Rising edge only
Rising edge only
IS11
IS10
IS01
IS00
0
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bits 1:0 = IS0[1:0] ei0 sensitivity
The interrupt sensitivity, defined using the IS0[1:0]
bits, is applied to the ei0 external interrupts:
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
EXTERNAL INTERUPT CONTROL REGISTER 1
(EICR1)
Read / Write
Reset Value: 0000 0000 (00h)
BIts 7:2 = Reserved
Bit 1 = TLIS Top Level Interrupt sensitivity
This bit configures the TLI edge sensitivity. It can
be set and cleared by software only when TLIE bit
is cleared.
0: Falling edge
1: Rising edge
Bit 0 = TLIE Top Level Interrupt enable
This bit allows to enable or disable the TLI capabil-
ity on the dedicated pin. It is set and cleared by
software.
0: TLI disabled
1: TLI enabled
Notes:
– A parasitic interrupt can be generated when
– In some packages, the TLI pin is not available. In
IS01 IS00
clearing the TLIE bit.
this case, the TLIE bit must be kept low to avoid
parasitic TLI interrupts.
0
0
1
1
7
0
0
1
0
1
0
0
External Interrupt Sensitivity
Falling edge & low level
Rising and falling edge
0
Falling edge only
Rising edge only
0
0
TLIS
ST72361
35/225
TLIE
0