C8051F902-GU Silicon Laboratories Inc, C8051F902-GU Datasheet - Page 237
![IC MCU 8BIT 8KB FLASH 24QSOP](/photos/12/15/121586/c8051f9xx_24-qsop_sml.jpg)
C8051F902-GU
Manufacturer Part Number
C8051F902-GU
Description
IC MCU 8BIT 8KB FLASH 24QSOP
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Specifications of C8051F902-GU
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
24-QSOP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 3.6 V
Data Converters
A/D 15x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
768 B
Interface Type
UART
Maximum Clock Frequency
25 MHz
Number Of Timers
4
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F912DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
Package
24QSOP
Device Core
8051
Family Name
C8051F90x
Maximum Speed
25 MHz
Data Bus Width
8 Bit
Number Of Programmable I/os
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1849-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F902-GU
Manufacturer:
SEMIKRON
Quantity:
45
Company:
Part Number:
C8051F902-GU
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
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SFR Definition 22.3. SMB0ADR: SMBus Slave Address
SFR Page = 0x0; SFR Address = 0xF4
SFR Definition 22.4. SMB0ADM: SMBus Slave Address Mask
SFR Page = 0x0; SFR Address = 0xF5
Name
Reset
Name
Reset
Bit
7
Bit
7
Type
Type
0
0
Bit
:
Bit
:
1
1
SLVM[6:0]
SLV[6:0]
EHACK
Name
Name
GC
7
0
7
1
SMBus Hardware Slave Address.
Defines the SMBus Slave Address(es) for automatic hardware acknowledgement.
Only address bits which have a 1 in the corresponding bit position in SLVM[6:0]
are checked against the incoming address. This allows multiple addresses to be
recognized.
General Call Address Enable.
When hardware address recognition is enabled (EHACK = 1), this bit will deter-
mine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
SMBus Slave Address Mask.
Defines which bits of register SMB0ADR are compared with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM[6:0] enables compari-
sons with the corresponding bit in SLV[6:0]. Bits set to 0 are ignored (can be either
0 or 1 in the incoming address).
Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
6
0
6
1
5
0
5
1
SLVM[6:0]
SLV[6:0]
R/W
R/W
Rev. 1.0
4
0
4
1
C8051F91x-C8051F90x
Function
Function
3
0
3
1
2
0
2
1
1
0
1
1
EHACK
R/W
R/W
GC
0
0
0
0
237
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