HD64F3672FXV Renesas Electronics America, HD64F3672FXV Datasheet - Page 151

IC H8/3672 MCU FLASH 48LQFP

HD64F3672FXV

Manufacturer Part Number
HD64F3672FXV
Description
IC H8/3672 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheets

Specifications of HD64F3672FXV

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
26
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
48-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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2.2.40 (2) NEG (W)
Notes
An overflow occurs if the previous contents of Rd was H'8000.
NEG (NEGate)
Operation
0 – Rd
Assembly-Language Format
NEG.W Rd
Operand Size
Word
Description
This instruction takes the two’s complement of the contents of a 16-bit register Rd (destination
operand) and stores the result in the 16-bit register Rd (subtracting the register contents from
H'0000). If the original contents of Rd was H'8000, however, the result remains H'8000.
Available Registers
Rd: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Register direct
Addressing
Mode
Rd
Mnemonic
NEG.W
Operands
Rd
1st byte
1
7
Condition Code
H: Set to 1 if there is a borrow at bit 11;
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Set to 1 if there is a borrow at bit 15;
2nd byte
9
otherwise cleared to 0.
cleared to 0.
cleared to 0.
cleared to 0.
otherwise cleared to 0.
Instruction Format
— —
Rev. 3.00 Dec 13, 2004 page 135 of 258
I
rd
UI
Section 2 Instruction Descriptions
H
3rd byte
U
Negate Binary Signed
N
4th byte
REJ09B0213-0300
Z
V
States
No. of
C
2

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