HD64F3672FXV Renesas Electronics America, HD64F3672FXV Datasheet - Page 45

• Manufacturer Part Number: HD64F3672FXV
• Description: IC H8/3672 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FXV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 48-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:
5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute
address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long
(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all
assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension.
A 24-bit absolute address can access the entire address space. Table 1.5 indicates the accessible
address ranges.
Table 1.5
For further details on the accessible range, see the relevant microcontroller hardware manual.
6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16),
or 32-bit (#xx:32) immediate data as an operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the second or fourth byte of the
instruction, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in the
second byte of the instruction, specifying a vector address.
8 bits
(@aa:8)
16 bits
(@aa:16)
24 bits
(@aa:24)
Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn), the lower 24 bits
of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or
longword access, the register value should be even.
Register indirect with pre-decrement—@–ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result becomes the address of a memory
operand. The result is also stored in the address register. The value subtracted is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the resulting
register value should be even.
Absolute Address Access Ranges
Normal Mode
H'FF00 to H'FFFF
(65,280 to 65,535)
H'0000 to H'FFFF
(0 to 65,535)
H'0000 to H'FFFF
(0 to 65,535)
Advanced Mode
H'FFFF00 to H'FFFFF
(16,776,960 to 16,777,215)
H'000000 to H'007FFF, H'FF8000 to H'FFFFFF
(0 to 32,767, 16,744,448 to 16,777,215)
H'00000 to H'FFFFF
(0 to 16,777,215)
Rev. 3.00 Dec 13, 2004 page 29 of 258
REJ09B0213-0300
Section 1 CPU