MC9S08LC36LH Freescale Semiconductor, MC9S08LC36LH Datasheet - Page 74

• Manufacturer Part Number: MC9S08LC36LH
• Description: IC MCU 36K FLASH 2K RAM 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08LC36LH

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 36KB (36K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 2x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: S08LC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2.5 KB
• Interface Type: I2C/SCI/SPI1/SPI2
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 18
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2-ch x 12-bit
• For Use With: DEMO9S08LC60 - BOARD DEMO FOR 9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
Chapter 5 Resets, Interrupts, and System Configuration
5.8.5
This register may be read at any time.
74
This bit can be written only one time after reset. Additional writes are ignored.
COPCLKS
BKGDPE
Reset
STOPE
RSTPE
COPE
COPT
Field
Field
ACIC
7
6
5
1
0
7
0
W
R
COPCLKS
System Options Register (SOPT2)
COP Watchdog Enable — This write-once bit defaults to 1 after reset.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
COP Watchdog Timeout — This write-once bit selects the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period.
0 Short timeout period selected.
1 Long timeout period selected.
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
Background Debug Mode Pin Enable — The BKGDPE bit enables the PTG0/BKGD/MS pin to function as
BKGD/MS. When the bit is clear, the pin will function as PTG0, which is an output-only general-purpose I/O. This
pin always defaults to BKGD/MS function after any reset.
0 BKGD pin disabled.
1 BKGD pin enabled.
Reset Pin Enable — This write-once bit when set enables the PTB2/RESET/ pin to function as
RESET. When clear, the pin functions as one of its input only alternative functions. This pin defaults to its
input-only port function following an MCU POR. Once configured for RESET pin, only POR can disable the
RESET pin function. When RSTPE is set, an internal pullup device is enabled on RESET.
0 PTB2/RESET/ pin functions as PTB2.
1 PTB2/RESET/ pin functions as RESET.
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
0 Internal 1-kHz clock is source to COP.
1 Bus clock is source to COP.
Analog Comparator to Input Capture Enable— This bit connects the output of ACMP to TPM1 input channel 0.
0 ACMP output not connected to TPM1 input channel 0
1 ACMP output connected to TPM1 input channel 0.
0
7
1
= Unimplemented or Reserved
0
0
6
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Figure 5-6. System Options Register (SOPT2)
Table 5-6. SOPT1 Field Descriptions
Table 5-7. SOPT2 Field Descriptions
0
0
5
0
0
4
Description
Description
3
0
0
0
0
2
Freescale Semiconductor
0
0
1
ACIC
0
0