HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 399
HD64F7047F50V
Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Specifications of HD64F7047F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7047F50V
Manufacturer:
PANJIT
Quantity:
30 000
Company:
Part Number:
HD64F7047F50V
Manufacturer:
RENESAS
Quantity:
386
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Part Number:
HD64F7047F50V
Manufacturer:
Renesas Electronics America
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Part Number:
HD64F7047F50V
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20 000
- Current page: 399 of 766
- Download datasheet (5Mb)
and clear TDRE flag in SSR to 0
as an output port with the PFC
Write transmit data to TDR
Clear TE bit in SCR to 0;
Read TDRE flag in SSR
Read TEND flag in SSR
All data transmitted?
Start transmission
select the TxD pin
Break output?
Clear DR to 0
Initialization
TDRE = 1
TEND = 1
Figure 12.7 Sample Serial Transmission Flowchart
<End>
Yes
Yes
Yes
Yes
No
No
No
No
[1]
[2]
[3]
[4]
[1] SCI initialization:
[2] SCI status check and transmit data
[3] Serial transmission continuation
[4] Break output at the end of serial
Set the TxD pin using the PFC.
After the TE bit is set to 1, 1 is
output for one frame, and
transmission is enabled. However,
data is not transmitted.
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear
the TDRE flag to 0. Checking and
clearing of the TDRE flag is
automatic when the DTC is
activated by a transmit data empty
interrupt (TXI) request, and data is
written to TDR.
transmission:
To output a break in serial
transmission, first clear the port
data register (DR) to 0, then clear
the TE bit to 0 in SCR and use the
PFC to select the TxD pin as an
output port.
Rev. 2.00, 09/04, page 357 of 720
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