HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 552
HD64F7047F50V
Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Specifications of HD64F7047F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
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Manufacturer:
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Rev. 2.00, 09/04, page 510 of 720
Bit
15
14
13
12
11 to 9 —
8
Bit Name
—
POE6F
POE5F
POE4F
PIE
Initial
Value
0
0
0
0
All 0
0
R/W
R
R/(W)*
R/(W)*
R/(W)*
R
R/W
Description
Reserved
This bit is always read as 0 and should only be written
with 0.
POE6 Flag
Indicates that a high impedance request has been input
to the POE6 pin.
[Clearing condition]
•
[Setting condition]
•
POE5 Flag
Indicates that a high impedance request has been input
to the POE5 pin.
[Clearing condition]
•
[Setting condition]
•
POE4 Flag
Indicates that a high impedance request has been input
to the POE4 pin.
[Clearing condition]
•
[Setting condition]
•
Reserved
These bits are always read as 0 and should only be
written with 0.
Port Interrupt Enable
Enables or disables an interrupt request when 1 is set in
any of bits POE4F to POE6F in ICSR2.
0: Interrupt request disabled
1: Interrupt request enabled
When 0 is written to POE6F after reading POE6F = 1
When the input set by bits 4 and 5 of ICSR2 occurs at
the POE6 pin
When 0 is written to POE5F after reading POE5F = 1
When the input set by bits 2 and 3 of ICSR2 occurs at
the POE5 pin
When 0 is written to POE4F after reading POE4F = 1
When the input set by bits 0 and 1 of ICSR2 occurs at
the POE4 pin
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