HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 427

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.1.3
The number of states (system clock cycles) S for the execution of one slot is calculated with the
following conditions:
As an example, figure 7.4 shows the flow of a pipeline in which the IF (memory access for
instruction fetch) of instructions 1 and 2 are two cycles, the MA (memory access for data access)
of instruction 1 is three cycles and all others are one cycle. The dashes indicate the instruction is
being stalled.
S = (the cycles of the stage with the highest number of cycles of all instruction stages
contained in the slot). This means that the instruction with the longest stage stalls others with
shorter stages.
The number of execution cycles for each stage:
Note: Same stage of another instruction is being executed in same slot.
IF
ID
EX
MA
WB/DSP Always one cycle
Instruction 1
Instruction 2
Slot Length
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5
The number of memory access cycles for instruction fetch
Always one cycle
Always one cycle
The number of memory access cycles for data access
(2)
IF
Figure 7.4 Slots Requiring Multiple Cycles
Figure 7.3 Impossible Pipeline Flow 2
IF
IF
IF
(2)
ID
IF
ID
ID
IF
—
IF
EX
EX
ID
IF
IF
EX
(1)
ID
MA
MA
EX
ID
ID
MA
(3)
EX
W/D
W/D
MA
EX
EX
MA
—
W/D
Rev. 5.00 Jun 30, 2004 page 411 of 512
MA
MA W/D
MA
—
W/D
W/D
MA
(1)
Section 7 Pipeline Operation
W/D
(1)
REJ09B0171-0500O
: Slot
Number of
cycles
: Slot