PIC12F635-E/P Microchip Technology, PIC12F635-E/P Datasheet - Page 128
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PIC12F635-E/P
Manufacturer Part Number
PIC12F635-E/P
Description
IC MCU FLASH 1KX14 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Specifications of PIC12F635-E/P
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
5
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-DIP (0.300", 7.62mm)
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
128Byte
Ram Memory Size
64Byte
Cpu Speed
20MHz
No. Of Timers
2
Processor Series
PIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
RS- 232, SPI, USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029, DV164101, DM163014
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM163029 - BOARD PICDEM FOR MECHATRONICSAC162057 - MPLAB ICD 2 HEADER 14DIPACICE0201 - MPLABICE 8P 300 MIL ADAPTER
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (4Mb)
PIC12F635/PIC16F636/639
REGISTER 11-6:
REGISTER 11-7:
DS41232D-page 126
bit 8
Legend:
R = Readable bit
-n = Value at POR
bit 8
bit 7
bit 6-5
bit 4-1
bit 0
Note
bit 8
Legend:
R = Readable bit
-n = Value at POR
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
AUTOCHSEL
COLPAR7
R/W-0
R/W-0
1:
Assured monotonic increment (or decrement) by design.
COLPAR7: Set/Cleared so that this 8th parity bit + the sum of the Configuration register row parity bits contain an odd
COLPAR6: Set/Cleared such that this 7th parity bit + the sum of the 7th bits in Configuration Registers 0 through 5 contain
COLPAR5: Set/Cleared such that this 6th parity bit + the sum of the 6th bits in Configuration Registers 0 through 5 contain
COLPAR4: Set/Cleared such that this 5th parity bit + the sum of the 5th bits in Configuration Registers 0 through 5 contain
COLPAR3: Set/Cleared such that this 4th parity bit + the sum of the 4th bits in Configuration Registers 0 through 5 contain
COLPAR2: Set/Cleared such that this 3rd parity bit + the sum of the 3rd bits in Configuration Registers 0 through 5 contain
COLPAR1: Set/Cleared such that this 2nd parity bit + the sum of the 2nd bits in Configuration Registers 0 through 5 contain
COLPAR0: Set/Cleared such that this 1st parity bit + the sum of the 1st bits in Configuration Registers 0 through 5 contain an
R6PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
AUTOCHSEL: Auto Channel Select bit
1 = Enabled – AFE selects channel(s) that has demodulator output “high” at the end of T
0 = Disabled – AFE follows channel enable/disable bits defined in Register 0
AGCSIG: Demodulator Output Enable bit, after the AGC loop is active
1 = Enabled – No output until AGC is regulating at around 20 mV
0 = Disabled – the AFE passes signal of any level it is capable of detecting
MODMIN<1:0>: Minimum Modulation Depth bit
00 = 50%
01 = 75%
10 = 25%
11 = 12%
LCZSEN<3:0>
0000 = -0dB (Default)
1111 = -30dB
R5PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
COLPAR6
R/W-0
AGCSIG
R/W-0
channel(s).
when the AGC begins regulating.
number of set bits.
an odd number of set bits.
an odd number of set bits.
an odd number of set bits.
an odd number of set bits.
an odd number of set bits.
an odd number of set bits.
odd number of set bits.
CONFIGURATION REGISTER 5
COLUMN PARITY REGISTER 6
:
W = Writable bit
‘1’ = Bit is set
(1)
W = Writable bit
‘1’ = Bit is set
COLPAR5
MODMIN1
: LCZ Sensitivity Reduction bit
R/W-0
R/W-0
COLPAR4
MODMIN0
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
COLPAR3
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
LCZSEN3
R/W-0
R/W-0
COLPAR2
LCZSEN2
R/W-0
R/W-0
PP
at input pins. The AGC Active Status bit is set
x = Bit is unknown
x = Bit is unknown
COLPAR1
LCZSEN1
R/W-0
R/W-0
© 2007 Microchip Technology Inc.
STAB
COLPAR0
LCZSEN0
; or otherwise, blocks the
R/W-0
R/W-0
R5PAR
R6PAR
R/W-0
R/W-0
bit 0
bit 0
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