AT80C51RD2-RLRUM Atmel, AT80C51RD2-RLRUM Datasheet - Page 34

• Manufacturer Part Number: AT80C51RD2-RLRUM
• Description: IC MCU 80C51 HI PERFORM 44VQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51RD2-RLRUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: AT80x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1280 B
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

11. Serial I/O Port
11.1
Figure 11-1. Framing Error Block diagram
Figure 11-2. UART Timings in Mode 1
34
Framing Error Detection
AT80C51RD2
SMOD0=X
SMOD0=1
The serial I/O port in the AT80C51RD2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as a Univer-
sal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and
3). Asynchronous transmission and reception can occur simultaneously and at different baud
rates
Serial I/O port includes the following enhancements:
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (see Figure 11-
1).
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (see
11-4) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only soft-
ware or a reset can clear FE bit. Subsequently, received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (see
11-2
RXD
• Framing error detection
• Automatic address recognition
FE
RI
and
Figure
SM 0/FE
SM OD1
Start
bit
1
11-3).
SM OD 0
D0
SM 1
D1
SM 2
-
D2
RE N
Se t FE bit if stop bit is 0 (fram ing erro r) (SM OD0 = 1)
SM 0 to UA RT m o de con tro l (SM OD0 = 0 )
PO F
To UA RT fra min g e rro r co nt ro l
D3
Data byte
TB8
GF1
D4
D5
RB8
GF0
D6
PD
TI
D7
IDL
RI
Stop
bit
S CO N (9 8h )
PCON (87 h)
4113D–8051–01/09
Figure
Table