ATTINY48-MMH Atmel, ATTINY48-MMH Datasheet - Page 80
![MCU AVR 4KB FLASH 12MHZ 28-VQFN](/photos/12/32/123209/28m1-vqfn_sml.jpg)
ATTINY48-MMH
Manufacturer Part Number
ATTINY48-MMH
Description
MCU AVR 4KB FLASH 12MHZ 28-VQFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY48-MMH
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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11. 8-bit Timer/Counter0
11.1
11.2
11.2.1
80
Features
Overview
ATtiny48/88
Definitions
•
•
•
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units. It allows accurate program execution timing (event management). A simplified
block diagram of the 8-bit Timer/Counter is shown in
I/O pins, refer to
bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed
in the
The PRTIM0 bit in
enable Timer/Counter0 module.
Figure 11-1. 8-bit Timer/Counter Block Diagram
Many register and bit references in this section are written in general form, where a lower case
“n” replaces the Timer/Counter number (in this case 0) and a lower case “x” replaces the Output
Compare Unit (in this case Compare Unit A or Compare Unit B). However, when using the regis-
Two Independent Output Compare Units
Clear Timer on Compare Match (Auto Reload)
Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
“8-bit Timer/Counter Register Description” on page
Timer/Counter
“Pinout of ATtiny48/88” on page
TCCRnA
OCRnA
TCNTn
OCRnB
“PRR – Power Reduction Register” on page 40
=
=
Count
Clear
Control Logic
TOP
=
Value
Fixed
TOP
2. CPU accessible I/O Registers, including I/O
clk
Tn
Figure
85.
11-1. For the actual placement of
TOVn
(Int.Req.)
Clock Select
OCnA (Int. Req.)
OCnB (Int. Req.)
( From Prescaler )
Detector
must be written to zero to
Edge
8008G–AVR–04/11
Tn
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