ATMEGA8A-AUR Atmel, ATMEGA8A-AUR Datasheet - Page 159
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ATMEGA8A-AUR
Manufacturer Part Number
ATMEGA8A-AUR
Description
MCU AVR 8KB FLASH 16MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8A-MU.pdf
(308 pages)
Specifications of ATMEGA8A-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Company
Part Number
Manufacturer
Quantity
Price
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19.10.4
8159D–AVR–02/11
UCSRC – USART Control and Status Register C
• Bit 0 – TXB8: Transmit Data Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDR.
The UCSRC Register shares the same I/O location as the UBRRH Register. See the
UBRRH/UCSRC Registers” on page 154
• Bit 7 – URSEL: Register Select
This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when
reading UCSRC. The URSEL must be one when writing the UCSRC.
• Bit 6 – UMSEL: USART Mode Select
This bit selects between Asynchronous and Synchronous mode of operation.
Table 19-4.
• Bit 5:4 – UPM1:0: Parity Mode
These bits enable and set type of Parity Generation and Check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting.
If a mismatch is detected, the PE Flag in UCSRA will be set.
Table 19-5.
• Bit 3 – USBS: Stop Bit Select
This bit selects the number of stop bits to be inserted by the trAnsmitter. The Receiver ignores
this setting.
Table 19-6.
Bit
Read/Write
Initial Value
UPM1
0
0
1
1
UMSEL
0
1
URSEL
UMSEL Bit Settings
UPM Bits Settings
USBS Bit Settings
R/W
USBS
7
1
0
1
UMSEL
R/W
6
0
UPM0
Mode
Asynchronous Operation
Synchronous Operation
0
1
0
1
UPM1
R/W
5
0
section which describes how to access this register.
UPM0
R/W
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
4
0
USBS
R/W
3
0
UCSZ1
R/W
Stop Bit(s)
2
1
1-bit
2-bit
UCSZ0
R/W
1
1
ATmega8A
UCPOL
R/W
0
0
“Accessing
UCSRC
159
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