ATMEGA8A-AUR Atmel, ATMEGA8A-AUR Datasheet - Page 51
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ATMEGA8A-AUR
Manufacturer Part Number
ATMEGA8A-AUR
Description
MCU AVR 8KB FLASH 16MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8A-MU.pdf
(308 pages)
Specifications of ATMEGA8A-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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12.2
12.2.1
8159D–AVR–02/11
Ports as General Digital I/O
Configuring the Pin
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
The ports are bi-directional I/O ports with optional internal pull-ups.
tional description of one I/O port pin, here generically called Pxn.
Figure 12-2. General Digital I/O
Note:
Each port pin consists of 3 Register bits: DDxn, PORTxn, and PINxn. As shown in
Description” on page
at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when a reset condition becomes
active, even if no clocks are running.
Pxn
1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
and PUD are common to all ports.
PUD:
SLEEP:
clk
I/O
:
65, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
(1)
SLEEP
SYNCHRONIZER
WDx:
RDx:
WPx:
RRx:
RPx:
D
L
Q
Q
D
PINxn
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
Q
Q
RESET
RESET
PORTxn
Q
Q
Q
Q
Figure 12-2
DDxn
CLR
CLR
D
D
ATmega8A
PUD
WDx
RDx
WPx
RRx
RPx
clk
shows a func-
I/O
I/O
, SLEEP,
“Register
51
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