ATMEGA8A-AUR Atmel, ATMEGA8A-AUR Datasheet - Page 172
ATMEGA8A-AUR
Manufacturer Part Number
ATMEGA8A-AUR
Description
MCU AVR 8KB FLASH 16MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8A-MU.pdf
(308 pages)
Specifications of ATMEGA8A-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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Price
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8159D–AVR–02/11
Figure 20-8. SCL Synchronization Between Multiple Masters
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting
data. If the value read from the SDA line does not match the value the Master had output, it has
lost the arbitration. Note that a Master can only lose arbitration when it outputs a high SDA value
while another Master outputs a low value. The losing Master should immediately go to Slave
mode, checking if it is being addressed by the winning Master. The SDA line should be left high,
but losing masters are allowed to generate a clock signal until the end of the current data or
address packet. Arbitration will continue until only one Master remains, and this may take many
bits. If several masters are trying to address the same Slave, arbitration will continue into the
data packet.
Figure 20-9. Arbitration Between Two Masters
Note that arbitration is not allowed between:
SCL from
SCL from
Master A
Master B
SCL Bus
Synchronized
Line
SCL Line
SDA from
SDA from
Master A
Master B
SDA Line
START
TA
Counting Low Period
low
Masters Start
TB
low
Arbitration, SDA
Master A Loses
TA
Counting High Period
high
Masters Start
TB
high
A
ATmega8A
SDA
172
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