TINY88-15MZ Atmel, TINY88-15MZ Datasheet - Page 170
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TINY88-15MZ
Manufacturer Part Number
TINY88-15MZ
Description
MCU AVR 8KB FLASH 12MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.TINY88-15MZ.pdf
(246 pages)
Specifications of TINY88-15MZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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17.6
17.6.1
170
Changing Channel or Reference Selection
ATtiny88 Automotive
ADC Input Channels
For a summary of conversion times, see
Table 17-1.
Bits MUXn and REFS0 in the ADMUX Register are single buffered through a temporary register
to which the CPU has random access. This ensures that the channels and reference selection
only takes place at a safe point during the conversion. The channel and reference selection is
continuously updated until a conversion is started. Once the conversion starts, the channel and
reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous
updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADC-
SRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is
written. The user is thus advised not to write new channel or reference selection values to
ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
In Single Conversion mode, always select the channel before starting the conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the conversion to complete before changing the channel selection.
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
Free Running conversions
• When ADATE or ADEN is cleared.
• During conversion, minimum one ADC clock cycle after the trigger event.
• After a conversion, before the Interrupt Flag used as trigger source is cleared.
ADC Conversion Time
Sample & Hold
(Cycles from Start of Conversion)
Table
17-1.
13.5
1.5
2.5
2
Conversion Time
(Cycles)
13.5
25
13
14
9157B–AVR–01/10
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