TINY88-15MZ Atmel, TINY88-15MZ Datasheet - Page 189
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
TINY88-15MZ
Manufacturer Part Number
TINY88-15MZ
Description
MCU AVR 8KB FLASH 12MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.TINY88-15MZ.pdf
(246 pages)
Specifications of TINY88-15MZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19.2
19.2.1
9157B–AVR–01/10
Register Description
SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Program memory operations.
• Bit 7 – Res: Reserved Bit
These bits are reserved and will always read zero.
• Bit 6 – RWWSB: Read-While-Write Section Busy
This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero
in ATtiny88.
• Bit 5 – Res: Reserved Bit
These bits are reserved and will always read zero.
• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be
cleared and the data will be lost.
• Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction within three cycles after RFLB and SELFPRGEN are set in the SPMCSR
Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register. See
details.
Bit
Read/Write
Initial Value
Wait_ee:
sbrc temp1, SELFPRGEN
rjmp Wait_spm
; input: spmcrval determines SPM action
; disable interrupts if enabled, store status
in
cli
; check that no EEPROM write access is present
sbic EECR, EEPE
rjmp Wait_ee
; SPM timed sequence
out
spm
; restore SREG (to enable interrupts if originally enabled)
out
ret
SPMCSR, spmcrval
SREG, temp2
temp2, SREG
R
7
0
-
RWWSB
R
6
0
“Reading the Fuse and Lock Bits from Software” on page 186
R
5
–
0
CTPB
R/W
4
0
RFLB
R/W
3
0
ATtiny88 Automotive
PGWRT
R/W
2
0
PGERS
R/W
1
0
SELFPRGEN
R/W
0
0
SPMCSR
189
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