TINY88-15MZ Atmel, TINY88-15MZ Datasheet - Page 180
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
TINY88-15MZ
Manufacturer Part Number
TINY88-15MZ
Description
MCU AVR 8KB FLASH 12MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.TINY88-15MZ.pdf
(246 pages)
Specifications of TINY88-15MZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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17.13.4
180
ATtiny88 Automotive
ADCSRB – ADC Control and Status Register B
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• Bit 7, 5:3 – Res: Reserved Bits
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when ADCSRB is written.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-
ger source that is cleared to a trigger source that is set, will generate a positive edge on the
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.
Table 17-6.
Bit
Read/Write
Initial Value
ADTS2
0
0
0
0
1
1
1
1
ADC Auto Trigger Source Selections
R
7
–
0
ACME
ADTS1
R/W
6
0
0
0
1
1
0
0
1
1
R
5
–
0
ADTS0
R
4
–
0
0
1
0
1
0
1
0
1
R
3
–
0
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter0 Compare Match A
Timer/Counter0 Overflow
Timer/Counter1 Compare Match B
Timer/Counter1 Overflow
Timer/Counter1 Capture Event
ADTS2
R/W
2
0
ADTS1
R/W
1
0
ADTS0
R/W
0
0
9157B–AVR–01/10
ADCSRB
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