PIC16F1937-E/ML Microchip Technology, PIC16F1937-E/ML Datasheet - Page 12
![IC PIC MCU FLASH 512KX14 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC16F1937-E/ML
Manufacturer Part Number
PIC16F1937-E/ML
Description
IC PIC MCU FLASH 512KX14 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16LF1933-ISS.pdf
(508 pages)
3.PIC16LF1933-ISS.pdf
(46 pages)
4.PIC16F1936-ISS.pdf
(2 pages)
5.PIC16F1936-ISS.pdf
(10 pages)
6.PIC16F1936-ISS.pdf
(40 pages)
7.PIC16F1936-ISS.pdf
(30 pages)
8.PIC16F1936-ISS.pdf
(12 pages)
9.PIC16LF1934-IML.pdf
(418 pages)
Specifications of PIC16F1937-E/ML
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
EUSART/MI2C/SPI
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
36
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
14-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
If your application needs to return without restoring the
context, the following code can be used:
Your application must handle context. This instruction
sequence will work because the instruction after setting
the GIE will always execute.
INDIRECT MEMORY ACCESS
Indirect memory accessing is using the FSR/INDF
registers to access parts of memory. In the legacy
PIC12/16, the FSR is 9 bits wide with the 9th bit stored
in STATUS as IRP. The enhanced PIC12/16 has a 16-
bit wide FSR with the Most Significant bits stored in the
FSRnH register. To access the entire RAM, the Most
Significant bits need to be adjusted. This is often done
with the BANKISEL macro. The BANKISEL macro
would set or clear the IRP bit as required. On the
enhanced PIC12/16, the BANKISEL macro will set or
clear each bit in FSRnH as required. This will take 8
instruction cycles. If you are willing to write to W, then
the update can be done in two cycles by MOVLW and
MOVWF or use ADDFSR, or MOVIW/WI with relative
offset.
MOVING FROM PIC18FXXX TO
PIC1XF1XXX
Moving back from the PIC18 to the enhanced PIC12/16
is different than moving forward from the legacy PIC12/
16. The enhanced PIC12/16 lacks some resources:
• 16 stack locations instead of 31
• Different FSR relative addressing mechanism
• No Multiply instructions
• Shorter CALL/GOTO reach
• 2 FSRs vs 3
Banking
Banking on the PIC18 is often misunderstood. The
PIC18 does have banking for the RAM accesses. It
also has a special bank that contains nearly all of the
SFRs. Each bank on the PIC18 is larger (256 bytes), so
the amount of time spent banking is reduced. The
enhanced PIC12/16 still has the 128-byte bank size
and no Access Bank. Converting the software requires
that the BANKSEL macro be used for many SFR
accesses and RAM accesses to assure the bank is
correctly configured.
DS41375A-page 12
(instructions instead of registers)
bsf INTCON,GIE
return
Paging
Paging is eliminated on the PIC18 by making the CALL
and
instruction payload gives CALL and GOTO the ability to
reach any instruction in memory. Simply adding a
PAGESEL before all CALLs and GOTOs will provide the
same capability to the enhanced PIC12/16 at the cost
of one cycle. The PIC18 relative branch (BRA) is also
present on the enhanced PIC12/16. In some cases, the
BRA will need to be replaced with a GOTO because the
reach of the PIC18 BRA is longer than the reach of the
PIC12/16 BRA.
All instruction addresses on a PIC18 are even because
the 16-bit instruction memory is byte addressed. This
may have an effect on the enhanced PIC12/16 conver-
sion as its program memory is word-addressed, so all
instructions are sequentially addressed.
INTERRUPTS
The PIC18 has a 2-level interrupt structure. The
interrupts have a fast context-save but the restore is
optional, depending upon the use of a fast return from
interrupt instruction. All interrupts will need to be
adjusted to understand the flat interrupt structure of the
enhanced PIC12/16 and all context restores will need
to be removed.
INDIRECT MEMORY ACCESS
The PIC18 has 3 FSRs, special registers for
addressing, and INDF SFRs for increment and
decrement. These can be replaced with the appropriate
use of the MOVIW
enhanced PIC12/16.
PROGRAM MEMORY TABLES
The PIC18 has table read instruction to retrieve 2 bytes
from program memory.
The enhanced PIC12/16 can retrieve 1 byte from pro-
gram memory by using the FSR/INDF to access the
program memory.
SOFTWARE OPTIMIZATION
After the software has been migrated to the enhanced
PIC12/16, the opportunity exists to increase the
performance by taking full advantage of the new
features. Software optimization for the enhanced
PIC12/16 can be classified as changes to the following
areas:
1.
2.
3.
4.
Arithmetic
ROM Table Access
RAM Buffer Access
Data Structures
GOTO two word instructions. The additional
and MOVWI instructions on the
© 2009 Microchip Technology Inc.