AT90USB82-16MUR Atmel, AT90USB82-16MUR Datasheet - Page 54

• Manufacturer Part Number: AT90USB82-16MUR
• Description: MCU AVR USB 8K FLASH 32-QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB82-16MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, PS/2, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART, debugWIRE
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

54
AT90USB82/162
While the WDT prescaler allows only even division factors (2, 4, 8...), the WDT peripheral also
includes a clock divider that directly acts on the clock source. This divider handles odd division
factors (3, 5, 7). In combination with the prescaler, a large number of time-out values can be
obtained.
The divider factor change is also ruled by the secure timed sequence : first the WDE and WDCE
bits must be set, and then four cycles are available to load the new divider value into the
WDTCKD register. Be aware that after this operation WDE will still be set. So keep in mind the
importance of order of operations. When setting up the WDT in Interrupt mode with specific val-
ues of prescaler and divider, the divider register must be loaded before the prescaler register :
1. In the same operation, write a logic one to the Watchdog change enable bits WDCE
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as
1. Set WDCE and WDE
2. Load the divider factor into WDTCKD
3. Wait WDCE being automatically cleared (just wait 2 more cycles)
4. Set again WDCE and WDE
5. Clear WDE, set WDIE and load the prescaler factor into WDTCSR in a same operation
6. Now the system is properly configured for Interrupt only mode. Inverting the two opera-
and WDE. A logic one must be written to WDE regardless of the previous value of the
WDE bit and even if it will be cleared after the operation.
desired, but with the WDCE bit cleared. This must be done in one operation.
tions would have been resulted into “Reset and Interrupt mode” and needed a third
operation to clear WDE.
7707F–AVR–11/10