ATMEGA16A-AUR Atmel, ATMEGA16A-AUR Datasheet - Page 249
ATMEGA16A-AUR
Manufacturer Part Number
ATMEGA16A-AUR
Description
MCU AVR 16KB FLASH 16MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16A-MU.pdf
(352 pages)
Specifications of ATMEGA16A-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA16A-AUR
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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24.7
24.8
24.8.1
8154B–AVR–07/09
Boundary-scan Description Language Files
Register Description
MCUCSR – MCU Control and Status Register
Table 24-8.
Notes:
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-scan Data Register are included in this description. A BSDL file for ATmega16A is
available.
The MCU Control and Status Register contains control bits for general MCU functions, and pro-
vides information on which reset source caused an MCU Reset.
• Bit 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this
bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of
the JTAG interface, a timed sequence must be followed when changing this bit: The application
software must write this bit to the desired value twice within four cycles to change its value.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to
one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
Bit
Read/Write
Initial Value
Bit Number
4
3
2
1
0
1. PRIVATE_SIGNAL1 should always be scanned in as zero.
2. PRIVATE:SIGNAL2 should always be scanned in as zero.
ATmega16A Boundary-scan Order (Continued)
JTD
R/W
7
0
Signal Name
PA1.Control
PA1.Pullup_Enable
PA0.Data
PA0.Control
PA0.Pullup_Enable
ISC2
R/W
6
0
R
5
–
0
JTRF
R/W
4
Module
WDRF
R/W
3
See Bit Description
BORF
R/W
2
EXTRF
R/W
1
ATmega16A
PORF
R/W
0
MCUCSR
249
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