PIC16LC433T-I/SO Microchip Technology, PIC16LC433T-I/SO Datasheet - Page 63

• Manufacturer Part Number: PIC16LC433T-I/SO
• Description: IC MCU CMOS 8BIT 10MHZ 2K 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC433T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: POR, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.7
The Watchdog Timer is a free running, on-chip RC oscil-
lator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will run,
even if the clock on the OSC1/CLKIN and OSC2/CLK-
OUT pins of the device has been stopped, for example,
by execution of a SLEEP instruction. During normal oper-
ation, a WDT time-out generates a device RESET
(Watchdog Timer Reset). If the device is in SLEEP
mode, a WDT time-out causes the device to wake-up
and continue with normal operation (Watchdog Timer
Wake-up). The WDT can be permanently disabled by
clearing configuration bit WDTE (Section 9.1).
9.7.1
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with tempera-
ture, V
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control, by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
FIGURE 9-16: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 9-8:
Address
2007h
81h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 9-1 for operation of these bits. Not all CP0 and CP1 bits are shown.
2001 Microchip Technology Inc.
Note: PSA and PS<2:0> are bits in the OPTION register.
DD
Watchdog Timer (WDT)
WDT PERIOD
and process variations from part to part (see
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Config. bits
OPTION
WDT Timer
Enable Bit
WDT
(1)
From TMR0 Clock Source
(Figure 7-5)
MCLRE
GPPU
Bit 7
Advance Information
0
1
INTEDG
PSA
Bit 6
CP1
M
U
X
T0CS
Bit 5
CP0
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out early and generating a premature
device RESET condition.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
9.7.2
It should also be taken into account that under worst
case conditions (V
Max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
See Example 7-1 and Example 7-2 for changing pres-
caler between WDT and Timer0.
0
Note:
PWRTE
Time-out
8 - to - 1 MUX
MUX
T0SE
Bit 4
WDT
Postscaler
WDT PROGRAMMING CONSIDERATIONS
When the prescaler is assigned to the
WDT, always execute a CLRWDT instruc-
tion before changing the prescale value,
otherwise a WDT Reset may occur.
1
8
WDTE
Bit 3
PSA
DD
PSA
To TMR0 (Figure 7-5)
= Min., Temperature = Max., and
FOSC2
Bit 2
PIC16C433
PS2
PS<2:0>
FOSC1
Bit 1
PS1
DS41139A-page 61
FOSC0
Bit 0
PS0