PIC16LF627A-I/ML Microchip Technology, PIC16LF627A-I/ML Datasheet
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PIC16LF627A-I/ML
Specifications of PIC16LF627A-I/ML
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PIC16LF627A-I/ML Summary of contents
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... Microcontrollers with nanoWatt Technology © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Flash-Based, 8-Bit CMOS Data Sheet DS40044G ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Device Flash (words) PIC16F627A 1024 PIC16F628A 2048 PIC16F648A 4096 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Low-Power Features: • Standby Current: - 100 nA @ 2.0V, typical • Operating Current μ kHz, 2.0V, typical - 120 μ MHz, 2.0V, typical • Watchdog Timer Current μA @ 2.0V, typical • ...
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... Pin Diagrams PDIP, SOIC RA2/AN2/V RA3/AN3/CMP1 RA4/T0CKI/CMP2 RA5/MCLR/V RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1 SSOP PIC16F627A/628A/648A DS40044G-page RA1/AN1 REF 17 RA0/AN0 RA7/OSC1/CLKIN 4 RA6/OSC2/CLKOUT RB7/T1OSI/PGD RB6/T1OSO/T1CKI/PGC 8 RB5 RB4/PGM 28-Pin QFN RA5/MCLR PIC16F627A/628A NC 4 PIC16F648A RB0/INT 7 21 RA7/OSC1/CLKIN 20 RA6/OSC2/CLKOUT RB7/T1OSI/PGD 15 RB6/T1OSO/T1CKI/PGC © 2009 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A DS40044G-page 5 ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 6 © 2009 Microchip Technology Inc. ...
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... The PIC16F627A/628A/648A family is supported by a full-featured macro assembler, a software simulator oscillator in-circuit emulator, a low cost in-circuit debugger, a low cost development programmer and a full-featured programmer. A Third Party “C” compiler support tool is also available. PIC16F628A PIC16F648A PIC16LF627A 20 20 2048 4096 1024 224 256 128 256 ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 8 © 2009 Microchip Technology Inc. ...
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... The devices are standard Flash devices, but with all program locations and configuration options already programmed by the factory. Certain code and prototype verification procedures production shipments are available. Please contact your Microchip Technology sales office for more details. 2.3 Serialized Quick-Turnaround- SM Production (SQTP ) Devices ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 10 © 2009 Microchip Technology Inc. ...
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... Program Data PIC16F627A 1024 x 14 224 x 8 PIC16F628A 2048 x 14 224 x 8 PIC16F648A 4096 x 14 256 x 8 PIC16LF627A 1024 x 14 224 x 8 PIC16LF628A 2048 x 14 224 x 8 PIC16LF648A 4096 x 14 256 x 8 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A The PIC16F627A/628A/648A can directly or indirectly address its register files or data memory ...
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... Power-up Timer Oscillator ALU Power-on 8 Reset Watchdog W Reg Timer Brown-out Reset Low-Voltage Timer1 Timer2 USART Data EEPROM PORTA RA0/AN0 RA1/AN1 RA2/AN2/V REF RA3/AN3/CMP1 RA4/T0CK1/CMP2 RA5/MCLR/V PP RA6/OSC2/CLKOUT RA7/OSC1/CLKIN PORTB RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1 RB4/PGM RB5 RB6/T1OSO/T1CKI/PGC RB7/T1OSI/PGD © 2009 Microchip Technology Inc. ...
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... RB1 RX DT RB2/TX/CK RB2 TX CK RB3/CCP1 RB3 CCP1 O = Output Legend: — = Not used TTL = TTL Input © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Input Type Output Type ST CMOS Bidirectional I/O port AN — Analog comparator input ST CMOS Bidirectional I/O port AN — Analog comparator input ...
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... Timer1 oscillator input ST CMOS ICSP data I/O Power — Ground reference for logic and I/O pins Power — Positive supply for logic and I/O pins CMOS = CMOS Output I = Input OD = Open Drain Output Description P = Power ST = Schmitt Trigger Input AN = Analog © 2009 Microchip Technology Inc. ...
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... All instructions are single cycle except for any program branches. These take two cycles since the fetch Note: instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4) ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 16 © 2009 Microchip Technology Inc. ...
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... Memory PIC16F628A and PIC16F648A On-chip Program Memory PIC16F648A only © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 4.2 Data Memory Organization The data memory (Figure 4-2 and Figure 4-3) is partitioned into four banks, which contain the General Purpose Registers (GPRs) and the Special Function Registers (SFRs) ...
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... TRISB 106h 186h 107h 187h 108h 188h 109h 189h 10Ah PCLATH 18Ah 10Bh INTCON 18Bh 10Ch 18Ch 10Dh 18Dh 10Eh 18Eh 10Fh 18Fh 11Fh 120h 14Fh 150h 1EFh 16Fh 1F0h 170h accesses 70h-7Fh 17Fh 1FFh Bank 3 © 2009 Microchip Technology Inc. ...
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... CMCON 20h General Purpose Register 80 Bytes 6Fh 70h 16 Bytes 7Fh Bank 0 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A (1) (1) Indirect addr. 80h TMR0 OPTION 81h PCL PCL 82h STATUS STATUS ...
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... T2CKPS1 T2CKPS0 -000 0000 54 — — — — 57 xxxx xxxx 57 xxxx xxxx CCP1M1 CCP1M0 57 --00 0000 OERR RX9D 74 0000 000x 79 0000 0000 82 0000 0000 — — — — — — — — CM1 CM0 63 0000 0000 © 2009 Microchip Technology Inc. ...
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... VREN VROE - = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Legend: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7. Note 1: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 T0CS T0SE ...
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... Microchip Technology Inc. ...
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... Unimplemented - = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Legend: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7. Note 1: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 T0CS T0SE ...
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... Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. R/W-0 R-1 R-1 RP1 RP0 Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-x R/W-x R/W bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A To achieve a 1:1 prescaler assignment for Note: TMR0, assign the prescaler to the WDT (PSA = 1). See Section 6.3.1 “Switching Prescaler Assignment”. R/W-1 R/W-1 R/W-1 ...
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... GIE (INTCON<7>). and R/W-0 R/W-0 R/W-0 T0IE INTE RBIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-x T0IF INTF RBIF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A R/W-0 R/W-0 U-0 RCIE TXIE — CCP1IE W = Writable bit U = Unimplemented bit, read as ‘ ...
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... R-0 R-0 U-0 R/W-0 RCIF TXIF — CCP1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
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... BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A BOR is unknown on Power-on Reset. It Note: must then be set by the user and checked on subsequent Resets to see if BOR is cleared, indicating a brown-out has occurred. The BOR Status bit is a “ ...
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... Example 4-1. EXAMPLE 4-1: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO RETLW or a INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue © 2009 Microchip Technology Inc. ...
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... RP1 RP0 6 from opcode bank select location select 00h RAM File Registers 7Fh Bank 0 For memory map detail see Figure 4-3, Figure 4-2 and Figure 4-1. Note: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Status Register 0 IRP bank select 180h Bank 1 Bank 2 ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 32 © 2009 Microchip Technology Inc. ...
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... When in this mode, the V very high-impedance output. The user must configure TRISA<2> bit as an input and use high-impedance loads. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A In one of the comparator modes defined by the CMCON register, pins RA3 and RA4 become outputs of the comparators. The TRISA< ...
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... Comparator Output WR PORTA CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA RD PORTA To Comparator DS40044G-page 34 PIN V DD RA2 Pin V SS (CMCON Reg.) Comparator Mode = 110 RA3 Pin Analog Input Mode V SS (CMCON Reg.) Schmitt Trigger Input Buffer D © 2009 Microchip Technology Inc. ...
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... Bit) MCLR circuit MCLR Filter Schmitt Trigger Program Input Buffer mode HV Detect Data Bus RD V TRISA PORTA © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Comparator Mode = 110 (CMCON Reg FIGURE 5-6: PIN PP From OSC1 CLKOUT(F OSC D WR PORTA OSC Data Latch ...
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... BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN To Clock Circuits Data Bus PORTA CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA F = 100, 101 (1) OSC RD PORTA Note 1: INTOSC with CLKOUT and INTOSC with I/O. DS40044G-page Schmitt Trigger Input Buffer RA7/OSC1/CLKIN Pin V SS © 2009 Microchip Technology Inc. ...
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... VRCON VREN VROE - = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition. Shaded cells Legend: are not used for PORTA. MCLRE configuration bit sets RA5 functionality. Note 1: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Output Type ST CMOS Bidirectional I/O port AN — ...
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... Polling of PORTB is not recommended while using the interrupt-on-change feature. FIGURE 5-8: BLOCK DIAGRAM OF RB0/INT PIN RBPU Data Bus PORTB CK Q Data Latch TRISB CK Q TRIS Latch TTL RD TRISB Input Buffer PORTB INT Schmitt Trigger © 2009 Microchip Technology Inc Weak Pull- RB0/INT V SS ...
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... Peripheral OE TTL Input RD TRISB Buffer PORTB USART Receive Input Schmitt Trigger Peripheral OE (output enable) is only active if Note 1: peripheral select is active. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A FIGURE 5-10 Weak RBPU Pull-up P SPEN V DD USART TX/CK Output Data Bus RB1/ RX/DT WR PORTB ...
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... CCP output 0 Data Bus PORTB CK Q Data Latch TRISB CK Q TRIS Latch (2) Peripheral OE RD TRISB PORTB CCP In Schmitt Trigger Peripheral OE (output enable) is only active if Note 1: peripheral select is active. DS40044G-page Weak Pull- RB3/ CCP1 V SS TTL Input Buffer © 2009 Microchip Technology Inc. ...
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... Data Latch D WR TRISB CK TRIS Latch RD TRISB LVP (Configuration Bit) RD PORTB PGM input Set RBIF From other RB<7:4> pins The low-voltage programming disables the interrupt-on-change and the weak pull-ups on RB4. Note: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Schmitt Trigger weak pull-up V ...
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... PIC16F627A/628A/648A FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN RBPU Data Bus PORTB CK Q Data Latch TRISB CK Q TRIS Latch RD TRISB RD PORTB Set RBIF From other RB<7:4> pins DS40044G-page weak DD P pull- TTL input buffer © 2009 Microchip Technology Inc. RB5 pin ...
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... FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI/PGC PIN RBPU Data Bus WR PORTB WR TRISB TRIS Latch RD TRISB T1OSCEN RD PORTB TMR1 Clock From RB7 Serial Programming Clock Set RBIF © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Data Latch Schmitt Trigger From other RB<7:4> pins weak pull-up ...
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... Data Bus WR PORTB WR TRISB RD TRISB T10SCEN RD PORTB Serial Programming Input Set RBIF DS40044G-page Data Latch TRIS Latch Q Q From other RB<7:4> pins weak pull-up P TMR1 oscillator V DD RB7/T1OSI/ PGD pin V SS TTL input buffer Schmitt Trigger © 2009 Microchip Technology Inc. ...
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... OPTION RBPU INTEDG u = unchanged unknown. Shaded cells are not used for PORTB. Legend: LVP configuration bit sets RB4 functionality. Note 1: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Output Type TTL CMOS Bidirectional I/O port. Can be software programmed for internal weak pull-up. ...
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... MOVF PORTB PORTB where T = instruction cycle and READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT PORTB<3:0> Outputs PORT latchPORT Pins ---------- ---------- ; ;01pp pppp 11pp pppp ; ;10pp pppp 11pp pppp ;10pp pppp 10pp pppp NOP Execute NOP = propagation delay of Q1 cycle PD © 2009 Microchip Technology Inc. ...
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... Timer0 module interrupt service routine before re- enabling this interrupt. The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut off during Sleep. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 6.2 Using Timer0 with External Clock When an external clock input is used for Timer0, it must meet certain requirements ...
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... WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. 0 SYNC Cycles 0 T0CS PSA WDT Postscaler/ TMR0 Prescaler 8 8-to-1MUX PS<2:0> 1 WDT Time-out 0 PSA Data Bus 8 TMR0 Reg Set flag bit T0IF on Overflow © 2009 Microchip Technology Inc. ...
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... Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used for Timer0. Legend: Option is referred by OPTION_REG in MPLAB Note 1: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This precaution must be taken even if the WDT is disabled ...
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... T1CKPS1 T1CKPS0 T1OSCEN (1) /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared (CCP) Module”). and RB6/T1OSO/T1CKI/PGC pins R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... TMR1 TMR1H T1OSC RB6/T1OSO/T1CKI/PGC RB7/T1OSI/PGD Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 7.2.1 EXTERNAL CLOCK INPUT TIMING FOR SYNCHRONIZED COUNTER MODE When an external clock input is used for Timer1 in Synchronized Counter mode, it must meet certain requirements ...
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... Reading ; the high and low bytes now will read a good ; value. ; MOVF TMR1H, W ;Read high byte MOVWF TMPH ; MOVF TMR1L, W ;Read low byte MOVWF TMPL ; ; Re-enable the Interrupts (if required) CONTINUE ;Continue with your ;code © 2009 Microchip Technology Inc. ...
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... T1CON — — T1CKPS1 x = unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module. Legend: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 7.5 Resetting Timer1 Using a CCP Trigger Output If the CCP1 module is configured in Compare mode to generate a “special event trigger” (CCP1M<3:0> = 1011), this signal will reset Timer1 ...
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... Synchronous Serial Port module which optionally uses it to generate shift clock. FIGURE 8-1: TIMER2 BLOCK DIAGRAM Sets flag TMR2 bit TMR2IF output Reset Prescaler TMR2 Reg 1:1, 1:4, 1:16 Postscaler Comparator 1:1 to 1:16 EQ T2CKPS<1:0> 4 PR2 Reg TOUTPS<3:0> © 2009 Microchip Technology Inc OSC 2 ...
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... TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 92h PR2 Timer2 Period Register x = unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module. Legend: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A R/W-0 R/W-0 R/W-0 TOUTPS0 W = Writable bit U = Unimplemented bit, read as ‘ ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 56 © 2009 Microchip Technology Inc. ...
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... Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 11xx = PWM mode Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A TABLE 9-1: CCP Mode Capture Compare PWM ...
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... CCP module off ; the new prescaler ; mode value and CCP ON ;Load CCP1CON with this ; value COMPARE MODE OPERATION BLOCK DIAGRAM Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Output Comparator Logic match TMR1H TMR1L CCP1CON<3:0> Mode Select © 2009 Microchip Technology Inc. ...
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... CCP1X x = unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1. Legend: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 9.2.4 SPECIAL EVENT TRIGGER In this mode (CCP1M<3:0>=1011), an internal hard- ware trigger is generated, which may be used to initiate an action ...
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... Module”) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM OUTPUT Period TMR2 = PR2 TMR2 = Duty Cycle [ ( ) ] 4 ⋅ ⋅ ⋅ = PR2 + 1 Tosc TMR2 prescale value © 2009 Microchip Technology Inc. ...
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... CCP1CON — — unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by PWM and Timer2. Legend: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Maximum PWM resolution (bits) for a given PWM frequency: PWM Resolution If the PWM duty cycle value is longer than ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 62 © 2009 Microchip Technology Inc. ...
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... CM<2:0>: Comparator Mode bits Figure 10-1 shows the comparator modes and CM<2:0> bit settings Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A The CMCON register, shown in Register 10-1, controls the comparator input and output multiplexers. A block two analog diagram of the comparator is shown in Figure 10-1 ...
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... CIS (CMCON<3>) is the Comparator Input Switch Off (Read as ‘0’ Off (Read as ‘0’ CIS = CIS = 1 C1V OUT CIS = 0 IN CIS = 1 C2V OUT From V REF Module C1V C1 OUT C2V C2 OUT CIS = CIS = 1 C1V OUT C2V OUT © 2009 Microchip Technology Inc. ...
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... Comparator Reference An external or internal reference signal may be used depending on the comparator Operating mode. The analog signal that is present compared to the IN signal and the digital output of the comparator IN is adjusted accordingly (Figure 10-2). © 2009 Microchip Technology Inc. PIC16F627A/628A/648A FIGURE 10- ...
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... FIGURE 10-3: MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM CnI NV To RA3/AN3/CMP1 or RA4/T0CK1/CMP2 pin To Data Bus CMCON<7:6> RD CMCON Set CMIF bit From other Comparator DS40044G-page 66 The Reset © 2009 Microchip Technology Inc. CnV OUT Q3 Q1 ...
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... Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 10.7 Comparator Operation During Sleep When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled ...
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... CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 R IC Value on Value on Bit 0 All Other POR Resets CM0 0000 0000 0000 0000 RBIF 0000 000x 0000 000u © 2009 Microchip Technology Inc. ...
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... VR<3:0>: V REF When VRR = 1: V When VRR = 0: V Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A The equations used to calculate the output of the Voltage Reference module are as follows: if VRR = 1: if VRR = 0: V REF The setting time of the Voltage Reference module must be considered when changing the V (Table 17-3) ...
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... Due to the limited drive capability, a buffer must be used in conjunction with the Voltage Reference module output for external connec- tions to V REF technique derived and DD REF R 8R VRR (From VRCON<3:0> Figure 11-2 shows an example buffering © 2009 Microchip Technology Inc. ...
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... VRCON VREN VROE 1Fh CMCON C2OUT C1OUT 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 - = Unimplemented, read as ‘0’. Legend: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Op Amp RA2 + Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 VRR — ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 72 © 2009 Microchip Technology Inc. ...
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... TX9D: 9th bit of transmit data. Can be parity bit. Note 1: SREN/CREN overrides TXEN in SYNC mode. Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous • Synchronous Bit SPEN (RCSTA<7>) and bits TRISB<2:1> have to be ...
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... R = Readable bit -n = Value at POR DS40044G-page 74 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADEN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... RX9 99h SPBRG Baud Rate Generator Register x = unknown unimplemented read as ‘0’. Shaded cells are not used for the BRG. Legend: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A EQUATION 12-1: Desired Baud Rate Calculated Baud Rate , the nearest (Calculated Baud Rate - Desired Baud Rate) ...
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... SPBRG value KBAUD ERROR (decimal) 0.303 +1.14% 26 1.170 -2.48 — — NA — — NA — — NA — — NA — — NA — — NA — — 8.192 — 0 0.032 — 255 © 2009 Microchip Technology Inc. ...
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... NA — — 300 NA — 500 NA — HIGH 55.93 — LOW 0.2185 — © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 16 MHz SPBRG value value KBAUD ERROR (decimal) — NA — — 255 1.202 +0.16% 207 129 2.404 +0.16% 103 32 9 ...
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... NA — — 625 — — 4 MHz SPBRG value KBAUD ERROR (decimal) 9615.385 0.160% 25 19230.77 0.160% 12 35714.29 -6.994% 6 62500 8.507% 3 125000 8.507% 1 250000 0.000 — — NA — — 32.768 kHz SPBRG value KBAUD ERROR (decimal © 2009 Microchip Technology Inc. ...
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... Note 1: The TSR register is not mapped in data memory not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data and the Baud Rate Generator (BRG) has produced a shift clock (Figure 12-1) ...
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... Transmit Shift Reg. (Transmit shift reg. empty flag) DS40044G-page 80 Data Bus TXREG register 8 MSb LSb (8) ² ² ² 0 TSR register TRMT TX9 TX9D bit 0 bit 1 Word 1 Pin Buffer and Control RB2/TX/CK pin SPEN bit 7/8 Stop bit © 2009 Microchip Technology Inc. ...
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... CMIE 98h TXSTA CSRC TX9 99h SPBRG Baud Rate Generator Register x = unknown unimplemented locations read as ‘0’. Legend: Shaded cells are not used for Asynchronous Transmission. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A bit 0 bit 1 Word 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RCIF TXIF — ...
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... FERR and RX9D information. OERR CREN ÷ 64 RSR register MSb or ÷ Stop (8) Data RX9 Recovery Enable Load of Receive Buffer RX9D RCREG register RCREG register RX9D RCIF Interrupt RCIE FERR LSb • • • Start FIFO 8 Data Bus © 2009 Microchip Technology Inc. ...
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... Note: (Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of bit 8. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Start Stop ...
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... CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 TXEN SYNC — BRGH TRMT Value on Value on Bit 0 all other POR Resets RX9D 0000 000x 0000 000x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 © 2009 Microchip Technology Inc. ...
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... SPBRG Baud Rate Generator Register x = unknown unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous Legend: reception. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A The ADEN bit will only take effect when the receiver is configured in 9-bit mode (RX9 = 1). When ADEN is disabled (= 0), all data bytes are received and the 9th bit can be used as the parity bit ...
Page 86
... If interrupts are desired, then set enable bit TXIE 9-bit transmission is desired, then set bit TX9. 6. Enable the transmission by setting bit TXEN 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 8. Start each transmission by loading data to the TXREG register. © 2009 Microchip Technology Inc. ...
Page 87
... Sync Master Mode; SPBRG = 0. Continuous transmission of two 8-bit words. Note: FIGURE 12-9: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RB1/RX/DT pin RB2/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 ADEN ...
Page 88
... CCP1IE TMR2IE TMR1IE -000 0000 — BRGH TRMT Value on: Value on all Bit 0 POR other Resets 0000 -000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 -000 -000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 © 2009 Microchip Technology Inc. ...
Page 89
... If enable bit TXIE is set, the interrupt will wake the chip from Sleep and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). © 2009 Microchip Technology Inc. PIC16F627A/628A/648A bit 2 bit 3 bit 4 bit 5 Follow these steps when setting up a Synchronous Slave Transmission: 1 ...
Page 90
... Value on Value on all POR other Resets 0000 -000 0000 000x 0000 000x 0000 0000 0000 0000 0000 -000 0000 -010 0000 -010 0000 0000 0000 0000 © 2009 Microchip Technology Inc. ...
Page 91
... EEADR: Specifies one of 128 locations of EEPROM Read/Write Operation Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles ...
Page 92
... EEPROM write sequence. U-0 U-0 U-0 R/W-x — — — WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/S-0 R/S-0 WREN WR RD bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 93
... After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set ...
Page 94
... EE writes ;enable interrupts (optional) © 2009 Microchip Technology Inc. ...
Page 95
... EECON2 EEPROM Control Register unknown unchanged unimplemented read as ‘0’ value depends upon condition. Legend: Shaded cells are not used by data EEPROM. EECON2 is not a physical register. Note 1: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 — — ...
Page 96
... PIC16F627A/628A/648A NOTES: DS40044G-page 96 © 2009 Microchip Technology Inc. ...
Page 97
... The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 14.1 Configuration Bits The configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘ ...
Page 98
... When MCLR is asserted in INTOSC mode, the internal clock oscillator is disabled. 4: Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = bit is set DS40044G-page 98 CPD LVP BOREN MCLRE FOSC2 (2) (1) DD (1) ( Unimplemented bit, read as ‘0’ ‘0’ = bit is cleared PWRTE WDTE F0SC1 F0SC0 bit bit is unknown © 2009 Microchip Technology Inc. ...
Page 99
... C2 PIC16F627A/628A/648A A series resistor may be required for AT strip cut Note 1: crystals. See Table 14-1 and Table 14-2 for recommended 2: values of C1 and C2. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A TABLE 14-1: Mode XT 455 kHz 2.0 MHz 4.0 MHz HS 8.0 MHz 16.0 MHz ...
Page 100
... AC/DC timing requirements listed in Section 17.6 “Timing Diagrams and Specifications”. Figure 14-4 below shows how an external clock circuit should be configured. FIGURE 14-4: EXTERNAL CLOCK INPUT OPERATION (EC, HS OSC CONFIGURATION) Clock from RA7/OSC1/CLKIN ext. system PIC16F627A/628A/648A RA6/OSC2/CLKOUT RA6 © 2009 Microchip Technology Inc. CLKIN PIC16F627A/ 628A/648A Z ...
Page 101
... The PIC16F627A/628A/648A can be configured to provide a clock out signal by programming the Configuration Word. The oscillator frequency, divided by 4 can be used for test purposes or to synchronize other logic. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 14.2.8 SPECIAL FEATURE: DUAL-SPEED OSCILLATOR MODES A software programmable dual-speed oscillator mode is provided when the PIC16F627A/628A/648A is configured in the INTOSC oscillator mode ...
Page 102
... BOREN OST/PWRT OST 10-bit Ripple-counter OSC1/ CLKIN Pin PWRT (1) On-chip 10-bit Ripple-counter OSC This is a separate oscillator from the INTOSC/RC oscillator. Note 1: DS40044G-page 102 See Table 14-3 for time out situations. Enable PWRT Enable OST © 2009 Microchip Technology Inc Chip_Reset R Q ...
Page 103
... Reset V DD Internal Reset 72 ms delay only if PWRTE bit is programmed to ‘0’. Note: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 14.4.3 OSCILLATOR START-UP TIMER (OST) The OST provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. Program execution will not start until the OST time out is complete ...
Page 104
... Illegal set on POR Illegal set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep may have DD Wake-up from Sleep PWRTE = 1 1024•T 1024•T OSC OSC — — 6 μs — © 2009 Microchip Technology Inc. ...
Page 105
... Interrupt Wake-up from Sleep u = unchanged unknown unimplemented bit, reads as ‘0’. Legend: Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 ...
Page 106
... Microchip Technology Inc. ...
Page 107
... Internal POR PWRT Time Out OST Time Out Internal Reset FIGURE 14-10: TIME OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR Internal POR PWRT Time Out OST Time Out Internal Reset © 2009 Microchip Technology Inc. PIC16F627A/628A/648A T PWRT T OST T PWRT T OST DD T PWRT ...
Page 108
... Transistor Q1 turns off when V 2: Internal Brown-out Reset should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor. pin break- DD EXTERNAL BROWN-OUT PROTECTION CIRCUIT MCLR 40k PIC16F627A/628A/648A is below a certain level such that 0 0 © 2009 Microchip Technology Inc. ...
Page 109
... Note 1: Some peripherals depend upon the system clock for operation. Since the system clock is suspended during Sleep, only those peripherals which do not depend upon the system clock will wake the part from Sleep. See Section 14.8.1 “Wake-up from Sleep”. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h ...
Page 110
... COMPARATOR INTERRUPT See Section 10.6 complete description of comparator interrupts (1) Interrupt Latency ( Inst ( — Dummy Cycle Inst (PC) . Synchronous latency = where for “Comparator Interrupts” 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) Dummy Cycle = instruction cycle time. CY © 2009 Microchip Technology Inc. ...
Page 111
... STATUS_TEMP,W;swap STATUS_TEMP register ;into W, sets bank to original ;state MOVWF STATUS ;move W into STATUS ;register SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0IE INTE RBIE T0IF INTF RCIF TXIF — ...
Page 112
... To TMR0 (Figure 6-1) PSA Value on Value on Bit 0 all other POR Reset Resets FOSC0 uuuu uuuu uuuu uuuu PS0 1111 1111 1111 1111 or V with no external DD SS should be disabled. I/O pins REF DD lowest current consumption. The ). IHMC © 2009 Microchip Technology Inc. ...
Page 113
... CPD bits by turning off the code protection. The entire data EEPROM and Flash program memory will be erased to turn the code protection off. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
Page 114
... It should be noted, that once the LVP bit is programmed to ‘0’, only High-Voltage Programming mode can be used to program the device. PP This mode allows the on the MCLR pin. IHH must be 5.0V +10% during erase on MCLR. The LVP bit IHH © 2009 Microchip Technology Inc. ...
Page 115
... TABLE 14-19: DEBUGGER RESOURCES I/O pins ICDCLK, ICDDATA Stack 1 level Program Memory Address 0h must be NOP 300h-3FEh The PIC16F648A-ICD device with header is supplied as an assembly. See Microchip Part Number AC162053. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A DS40044G-page 115 ...
Page 116
... PIC16F627A/628A/648A NOTES: DS40044G-page 116 © 2009 Microchip Technology Inc. ...
Page 117
... Destination select store result store result in file register f. Default Time-out bit PD Power-down bit © 2009 Microchip Technology Inc. PIC16F627A/628A/648A The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations ...
Page 118
... TO,PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk © 2009 Microchip Technology Inc. ...
Page 119
... Words: 1 Cycles: 1 Example ADDWF REG1, 0 Before Instruction W = 0x17 REG1 = 0xC2 After Instruction W = 0xD9 REG1 = 0xC2 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A ANDLW k Syntax: Operands: Operation: Status Affected: kkkk kkkk Encoding: Description: Words: Cycles: Example ANDWF Syntax: f,d Operands: Operation: Status Affected: ...
Page 120
... NOP is executed instead, making this a two-cycle instruction. 1 1(2) HERE BTFSC REG1 FALSE GOTO PROCESS_CODE TRUE • • • Before Instruction PC = address HERE After Instruction if REG<1> address TRUE if REG<1> = address FALSE © 2009 Microchip Technology Inc. ...
Page 121
... BTFSS FALSE GOTO TRUE • • • Before Instruction PC = address HERE After Instruction if FLAG<1> address FALSE if FLAG<1> address TRUE © 2009 Microchip Technology Inc. PIC16F627A/628A/648A CALL Syntax: Operands: Operation: Status Affected: bfff ffff Encoding: Description: Words: Cycles: REG1 Example PROCESS_CODE CLRF ...
Page 122
... Decrement register ‘f’. If ‘d’ is ‘0’. the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’ DECF CNT, 1 Before Instruction CNT = 0x01 After Instruction CNT = 0x00 © 2009 Microchip Technology Inc. ...
Page 123
... CONTINUE • • • Before Instruction PC = address After Instruction REG1 = REG1 - 1 if REG1 = address CONTINUE if REG1 ≠ address HERE+1 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A GOTO Syntax: Operands: Operation: skip if result = Status Affected: Encoding: dfff ffff Description: Words: Cycles: Example REG1, 1 ...
Page 124
... A NOP is executed instead making it a two-cycle instruction. 1 1(2) HERE INCFSZ REG1, 1 GOTO LOOP CONTINUE • • • Before Instruction PC = address HERE After Instruction REG1 = REG1 + 1 if CNT = address CONTINUE if REG1≠ address HERE +1 © 2009 Microchip Technology Inc. ...
Page 125
... Words: 1 Cycles: 1 Example IORWF REG1, 0 Before Instruction REG1 = 0x13 W = 0x91 After Instruction REG1 = 0x13 W = 0x93 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A MOVLW Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: Example MOVF f,d Syntax: Operands: ...
Page 126
... GIE None 00 0000 0000 1001 Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two- cycle instruction RETFIE After Interrupt PC = TOS GIE = 1 © 2009 Microchip Technology Inc. ...
Page 127
... POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. Words: 1 Cycles: 2 Example RETURN After Interrupt PC = TOS © 2009 Microchip Technology Inc. PIC16F627A/628A/648A RLF Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: ...
Page 128
... The W register is subtracted (2’s complement method) from the eight- bit literal ‘k’. The result is placed in the W register SUBLW 0x02 Before Instruction After Instruction result is positive Before Instruction After Instruction result is zero Before Instruction After Instruction W = 0xFF result is negative © 2009 Microchip Technology Inc. ...
Page 129
... REG1 = result is zero Example 3: Before Instruction REG1 = After Instruction REG1 = 0xFF result is negative © 2009 Microchip Technology Inc. PIC16F627A/628A/648A SWAPF Syntax: Operands: Operation: Status Affected: Encoding: dfff ffff Description: Words: Cycles: Example TRIS Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: ...
Page 130
... W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’ XORWF REG1, 1 Before Instruction REG1 = 0xAF W = 0xB5 After Instruction REG1 = 0x1A W = 0xB5 © 2009 Microchip Technology Inc. ...
Page 131
... MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 16.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
Page 132
... Support for the entire device instruction set ® standard HEX • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility © 2009 Microchip Technology Inc. ...
Page 133
... Microchip Technology Inc. PIC16F627A/628A/648A 16.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- chip's most cost effective high-speed hardware ...
Page 134
... This usually includes a single application and debug capability, all for DDMAX on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® © 2009 Microchip Technology Inc. ...
Page 135
... Exposure to maximum rating conditions for extended periods may affect device reliability. Voltage spikes below V Note: SS Thus, a series resistor of 50-100 pulling this pin directly to V © 2009 Microchip Technology Inc. PIC16F627A/628A/648A ............................................................................................-0.3 to +14V SS ....................................................................................-0. )..................................................................................................................... ± )............................................................................................................... ± ...
Page 136
... FIGURE 17-1: 6.0 5.5 5.0 4 (VOLTS) 4.0 3.5 3.0 2.5 0 The shaded region indicates the permissible combinations of voltage and frequency. Note: PIC16LF627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C FIGURE 17-2: 6.0 5.5 5.0 4 (VOLTS) 4.0 3.5 3.0 2.5 2.0 0 The shaded region indicates the permissible combinations of voltage and frequency. ...
Page 137
... DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended) PIC16LF627A/628A/648A (Industrial) PIC16LF627A/628A/648A (Industrial) PIC16F627A/628A/648A (Industrial, Extended) Param Sym Characteristic/Device No Supply Voltage D001 PIC16LF627A/628A/648A PIC16F627A/628A/648A D002 V DR RAM Data Retention (1) Voltage D003 V POR V Start Voltage DD to ensure Power-on Reset D004 S VDD V Rise Rate DD to ensure Power-on Reset ...
Page 138
... PIC16F627A/628A/648A 17.2 DC Characteristics: PIC16F627A/628A/648A (Industrial) PIC16LF627A/628A/648A (Industrial) DC CHARACTERISTICS Param LF and F Device No. Characteristics Supply Voltage ( D001 LF/F Power-down Base Current ( D020 LF/F (1) Peripheral Module Current (ΔI ) MOD LF D021 LF/F LF/F D022 LF D023 LF/F LF D024 LF/F LF D025 LF/F Supply Current ( D010 LF/F LF D011 ...
Page 139
... The “Δ” current is the additional current consumed when this peripheral is enabled. This current should be Note 1: added to the base consumption. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Standard Operating Conditions (unless otherwise stated) -40°C ≤ Ta ≤ +125°C for extended Operating temperature Min† Typ ...
Page 140
... V, -40° to +85° 7.0 mA 4.5 V, +85° +125° -3.0 mA 4.5 V, -40° to +85° -2.5 mA 4.5 V, +85° +125°C V RA4 pin PIC16F627A/628A/648A, PIC16LF627A/628A/648A pF In XT, HS and LP modes when external clock used to drive OSC1. pF © 2009 Microchip Technology Inc. ...
Page 141
... Refer to Section 13.7 “Using the Data EEPROM” for a more detailed discussion on data EEPROM Note 1: endurance. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A PIC16LF627A/628A/648A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and -40°C ≤ TA ≤ +125°C for extended Operating voltage V ...
Page 142
... DD -85° to +125° 2.0V to 3.0V DD -40° to +85°C s μ Units Comments LSb Low Range (VRR = 1) LSb High Range (VRR = 0) LSb Low Range (VRR = 1) LSb High Range (VRR = 0) Ω s μ output signal on RA2 REF © 2009 Microchip Technology Inc. ...
Page 143
... Uppercase letters and their meanings Fall H High I Invalid (High-impedance) L Low FIGURE 17-3: LOAD CONDITIONS Load Condition 1 Pin R = 464Ω for all pins except OSC2 for OSC2 output © 2009 Microchip Technology Inc. PIC16F627A/628A/648A T osc Load Condition Pin V SS Time OSC1 T0CKI ...
Page 144
... XT and RC Osc mode ns HS, EC Osc mode μs LP Osc mode ns RC Osc mode ns XT Osc mode ns HS Osc mode μs LP Osc mode ns INTOSC mode (fast) μs INTOSC mode (slow 4/F CY OSC ns XT oscillator, T L/H duty OSC cycle — 5.0V DD © 2009 Microchip Technology Inc. ...
Page 145
... Legend: TBD = To Be Determined. * Characterized but not tested. FIGURE 17-5: CLKOUT AND I/O TIMING Q4 OSC1 CLKOUT I/O Pin (input) I/O Pin Old Value (output) © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Min Typ Max Units — 4 — MHz 3.96 4 4.04 MHz V MHz 2.0V ≤ ...
Page 146
... PIC16LF62XA — PIC16F62XA — PIC16LF62XA — — PIC16F62XA T +200 ns* OSC PIC16LF62XA T +400 ns* OSC 0 PIC16F62XA — PIC16LF62XA — 100* 200 © 2009 Microchip Technology Inc. Typ† Max Units 75 200* ns — 400 200* ns — 400 100* ns — 200 100* ns — 200* ns — ...
Page 147
... Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI/CMP2 RB6/T1OSO/T1CKI/PGC TMR0 OR TMR1 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A V BOR 35 Min Typ† Max ...
Page 148
... OSC — ns — ns — ns — ns — prescale value (2, 4, ..., 256) — ns — ns — ns — ns — ns — ns — ns — ns — ns — ns — prescale value ( — — — ns — ns (1) — kHz 7T — OSC © 2009 Microchip Technology Inc. ...
Page 149
... T F CCP output fall time CC * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Min ...
Page 150
... PIC16F627A/628A/648A NOTES: DS40044G-page 150 © 2009 Microchip Technology Inc. ...
Page 151
... FIGURE 18-1: TYPICAL BASELINE I 160 140 120 100 2.0 2.5 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A ° ° vs -40°C 0°C +25°C 3.0 3.5 4 ...
Page 152
... TYPICAL BASELINE CURRENT I 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 2.0 2.5 3.0 DS40044G-page 152 ° vs +85°C 3.0 3.5 4.0 V (Volts) DD vs. V (125 PD DD +125°C 3.5 4.0 4.5 V (Volts) DD 4.5 5.0 5.5 ° C) 5.0 5.5 © 2009 Microchip Technology Inc. ...
Page 153
... FIGURE 18-4: TYPICAL BOR 4.5 4.6 4.7 FIGURE 18-5: TYPICAL SINGLE COMPARATOR 2.5 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A vs 4.8 4.9 5.0 5.1 5.2 V (Volts 3.5 4 4.5 V (Volts) DD 125°C 85°C 25°C 0°C -40°C 5.3 5.4 5.5 125°C 85°C 25° ...
Page 154
... FIGURE 18-7: TYPICAL WDT 2.0 2.5 3.0 DS40044G-page 154 I vs 3.5 4.0 4.5 V (Volts 3.5 4.0 4.5 V (Volts) DD 125°C 85°C 25°C 0°C -40°C 5.0 5.5 125°C 85°C 25°C 0°C -40°C 5.0 5.5 © 2009 Microchip Technology Inc. ...
Page 155
... FIGURE 18-8: AVERAGE 2.5 FIGURE 18-9: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE VOLTS DD 5.0% 4.0% 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% -40 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A _TIMER1 3 3.5 4 4 Temperature (ºC) -40C 0C 25C 85C 125 5 5.5 125 DS40044G-page 155 ...
Page 156
... FIGURE 18-11: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE VOLTS DD 5.0% 4.0% 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% -40 DS40044G-page 156 25 85 Temperature (º Temperature (ºC) 125 125 © 2009 Microchip Technology Inc. ...
Page 157
... FIGURE 18-13: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. V -40°C TO 85°C 5.0% 4.0% 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% 2 2.5 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 3 3.5 4 4 3.5 4 4 25°C – 4 MHz MODE DD 5 5.5 ...
Page 158
... INTERNAL OSCILLATOR I 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 2 2.5 FIGURE 18-15: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. V MODE 2.5 DS40044G-page 158 vs. V – 4 MHz MODE Avg - 3.5 4 4 5.5 AT 25°C – SLOW DD 4.5 5 5.5 © 2009 Microchip Technology Inc. ...
Page 159
... FIGURE 18-17: SUPPLY CURRENT (I 500 450 400 350 300 250 200 150 100 2.0 2.5 3.0 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A vs. V – SLOW MODE Avg - 3.5 4 4.5 V ( MHz (XT OSCILLATOR MODE OSC 3.5 4.0 4 ...
Page 160
... MHz (XT OSCILLATOR MODE OSC 3.0 3.5 4.0 4.5 V (Volts vs MHz (HS OSCILLATOR MODE OSC 4.9 5.0 5.1 5.2 V (Volts) DD 125°C 85°C 25°C 0°C -40°C 5.0 5.5 125°C 85°C 25°C 0°C -40°C 5.3 5.4 5.5 © 2009 Microchip Technology Inc. ...
Page 161
... FIGURE 18-20: TYPICAL WDT PERIOD vs 2.5 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A (-40°C TO +125°C) DD WDT Time-out 3 3.5 4 4.5 V ( 125 5 5.5 DS40044G-page 161 ...
Page 162
... PIC16F627A/628A/648A NOTES: DS40044G-page 162 © 2009 Microchip Technology Inc. ...
Page 163
... Note : In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Example PIC16F627A -I/P ...
Page 164
... PIC16F627A/628A/648A N NOTE DS40044G-page 164 © 2009 Microchip Technology Inc. ...
Page 165
... D N NOTE © 2009 Microchip Technology Inc. PIC16F627A/628A/648A α φ A2 β DS40044G-page 165 ...
Page 166
... PIC16F627A/628A/648A DS40044G-page 166 © 2009 Microchip Technology Inc. ...
Page 167
... D N NOTE © 2009 Microchip Technology Inc. PIC16F627A/628A/648A φ L DS40044G-page 167 ...
Page 168
... PIC16F627A/628A/648A D TOP VIEW A3 DS40044G-page 168 EXPOSED PAD NOTE 1 BOTTOM VIEW © 2009 Microchip Technology Inc. ...
Page 169
... Microchip Technology Inc. PIC16F627A/628A/648A DS40044G-page 169 ...
Page 170
... PIC16F627A/628A/648A NOTES: DS40044G-page 170 © 2009 Microchip Technology Inc. ...
Page 171
... Replaced Package Drawings (Rev. AM); Replaced Development Support Section; Revised Product ID System. Revision G (10/2009) Corrected 28-lead QFN Package in Section 19.1. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A APPENDIX B: The differences between the PIC16F627A/628A/648A devices listed in this data sheet are shown in Table B-1. TABLE B-1: ...
Page 172
... These differences may cause this device to perform differently in your application than the earlier version of this device. MIGRATING FROM ® OTHER PIC DEVICES web site for availability web site for availability © 2009 Microchip Technology Inc. ...
Page 173
... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • ...
Page 174
... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS40044G-page 174 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS40044G © 2009 Microchip Technology Inc. ...
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... Compare Mode. See Compare PWM Mode. See PWM Timer Resources......................................................... 57 CCP1CON Register ............................................................ 57 CCP1M Bits ................................................................ 57 CCP1X:CCP1Y Bits .................................................... 57 CCP2CON Register CCP2M<3:2> Bits ....................................................... 57 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A CCP2X:CCP2Y Bits.................................................... 57 Clocking Scheme/Instruction Cycle .................................... 15 CLRF Instruction............................................................... 121 CLRW Instruction.............................................................. 122 CLRWDT Instruction......................................................... 122 CMCON Register................................................................ 63 Code Examples Data EEPROM Refresh Routine ...
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... Power-Down Mode (Sleep)............................................... 112 Power-On Reset (POR) .................................................... 103 Power-up Timer (PWRT) .................................................. 103 PR2 Register ................................................................ 54, 60 Program Memory Organization........................................... 17 PWM (CCP Module) ........................................................... 60 Block Diagram ............................................................ 60 Simplified PWM .................................................. 60 CCPR1H:CCPR1L Registers...................................... 60 Duty Cycle .................................................................. 61 Example Frequencies/Resolutions ............................. 61 Period ......................................................................... 60 Set-Up for PWM Operation......................................... 61 TMR2 to PR2 Match ................................................... 60 © 2009 Microchip Technology Inc. ...
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... External Clock Input.................................................... 47 Interrupt....................................................................... 47 Prescaler..................................................................... 48 Switching Prescaler Assignment................................. 49 Timer0 Module ............................................................ 47 Timer1 Asynchronous Counter Mode ..................................... 52 Capacitor Selection..................................................... 53 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A External Clock Input ................................................... 51 External Clock Input Timing........................................ 52 Oscillator..................................................................... 53 Prescaler .............................................................. 51, 53 Resetting Timer1 ........................................................ 53 Resetting Timer1 Registers ........................................ 53 Special Event Trigger (CCP) ...................................... 59 Synchronized Counter Mode ...
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... PIC16F627A/628A/648A Synchronous Slave Transmit ...................................... 89 V Voltage Reference Configuration............................................................... 69 Voltage Reference Module ......................................... 69 W Watchdog Timer (WDT) .................................................... 111 WWW Address.................................................................. 173 WWW, On-Line Support........................................................ 5 X XORLW Instruction ........................................................... 130 XORWF Instruction ........................................................... 130 DS40044G-page 178 © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC16F627A/628A/648A XXX Examples: a) PIC16F627A - E/P 301 = Extended Pattern Temp., PDIP package, 20 MHz, normal V its, QTP pattern #301. range 3. PIC16LF627A - I/SO = Industrial Temp., SOIC package, 20 MHz, extended V range 3.0V to 5.5V DD limits. range 2.0V to 5.5V DD range 2.0V to 5.5V DD lim DS40044G-page 179 ...
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... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...