PIC16LF627A-I/ML Microchip Technology, PIC16LF627A-I/ML Datasheet - Page 83
![IC MCU FLASH 1KX14 EEPROM 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF627A-I/ML
Manufacturer Part Number
PIC16LF627A-I/ML
Description
IC MCU FLASH 1KX14 EEPROM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF627A-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
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FIGURE 12-5:
FIGURE 12-6:
FIGURE 12-7:
© 2009 Microchip Technology Inc.
RB1/RX/DT (Pin)
RB1/RX/DT (pin)
RB1/RX/DT (pin)
RCV Shift Reg
RCV Shift Reg
RCV Buffer Reg
Read RCV
Buffer Reg
RCREG
RCIF
(interrupt flag)
ADEN = 1
(Address Match
RCV Buffer Reg
Read RCV
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
ADEN = 1
(Address Match
RCV Shift
Reg
RCV Buffer Reg
Read RCV
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
ADEN
(Address Match
Note:
Note:
Enable)
Enable)
Enable)
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(Receive Buffer) because ADEN = 1 and bit 8 = 0.
This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG
(receive buffer) because ADEN was not updated (still = 1) and bit 8 = 0.
This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG
(Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents
of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of bit 8.
‘1’
‘1’
Start
Start
Start
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY
VALID DATA BYTE
bit
bit
bit
bit 0
bit 0
bit 0
bit 8 = 1, Address Byte
bit 8 = 1, Address Byte
bit 8 = 0, Data Byte
bit 1
bit 1
bit 1
bit 8
bit 8
bit 8
Stop
Stop
Stop
bit
bit
bit
Word 1
RCREG
Word 1
RCREG
PIC16F627A/628A/648A
Start
Start
Start
bit
bit
bit
bit 8 = 1, Address Byte
bit 0
bit 0
bit 0
bit 8 = 0, Data Byte
bit 8 = 0, Data Byte
bit 8
bit 8
bit 8
Stop
Stop
Stop
bit
bit
bit
Word 2
RCREG
Word 1
RCREG
DS40044G-page 83
‘1’
‘1’
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