PIC16LF627A-I/ML Microchip Technology, PIC16LF627A-I/ML Datasheet - Page 26
![IC MCU FLASH 1KX14 EEPROM 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF627A-I/ML
Manufacturer Part Number
PIC16LF627A-I/ML
Description
IC MCU FLASH 1KX14 EEPROM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF627A-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
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PIC16F627A/628A/648A
4.2.2.3
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See
Section 4.2.2.5 “PIR1 Register” for a description of
the comparator enable and flag bits.
REGISTER 4-3:
DS40044G-page 26
Section 4.2.2.4
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INTCON Register
INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB<7:4> pins changes state (must be cleared in software)
0 = None of the RB<7:4> pins have changed state
Legend:
R = Readable bit
-n = Value at POR
R/W-0
GIE
“PIE1
Register”
R/W-0
PEIE
R/W-0
T0IE
and
W = Writable bit
‘1’ = Bit is set
R/W-0
INTE
Note:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
RBIE
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
R/W-0
© 2009 Microchip Technology Inc.
T0IF
x = Bit is unknown
R/W-0
INTF
R/W-x
RBIF
bit 0
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