PIC16LF627A-I/ML Microchip Technology, PIC16LF627A-I/ML Datasheet - Page 109
![IC MCU FLASH 1KX14 EEPROM 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF627A-I/ML
Manufacturer Part Number
PIC16LF627A-I/ML
Description
IC MCU FLASH 1KX14 EEPROM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF627A-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
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14.5
The PIC16F627A/628A/648A has 10 sources of
interrupt:
• External Interrupt RB0/INT
• TMR0 Overflow Interrupt
• PORTB Change Interrupts (pins RB<7:4>)
• Comparator Interrupt
• USART Interrupt TX
• USART Interrupt RX
• CCP Interrupt
• TMR1 Overflow Interrupt
• TMR2 Match Interrupt
• Data EEPROM Interrupt
The Interrupt Control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on Reset.
The “return-from-interrupt” instruction,
interrupt routine as well as sets the GIE bit, which re-
enables RB0/INT interrupts.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag is contained in the special
register PIR1. The corresponding interrupt enable bit is
contained in special registers PIE1.
FIGURE 14-14:
© 2009 Microchip Technology Inc.
TMR1IF
TMR1IE
TMR2IF
TMR2IE
CCP1IF
CCP1IE
CMIF
CMIE
RCIF
RCIE
EEIF
EEIE
TXIF
TXIE
Note 1: Some peripherals depend upon the system clock for operation. Since the system clock is
Interrupts
suspended during Sleep, only those peripherals which do not depend upon the system
clock will wake the part from Sleep. See Section 14.8.1 “Wake-up from Sleep”.
INTERRUPT LOGIC
RETFIE
RBIF
RBIE
PEIE
INTF
INTE
T0IF
T0IE
, exits
PIC16F627A/628A/648A
GIE
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid RB0/
INT recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 14-15).
The latency is the same for one or two-cycle instructions.
Once in the interrupt service routine, the source(s) of the
interrupt can be determined by polling the interrupt flag
bits. The interrupt flag bit(s) must be cleared in software
before re-enabling interrupts to avoid multiple interrupt
requests.
Note 1: Individual interrupt flag bits are set
2: When an instruction that clears the GIE
regardless
corresponding mask bit or the GIE bit.
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a NOP
in the cycle immediately following the
instruction which clears the GIE bit. The
interrupts which were ignored are still
pending to be serviced when the GIE bit
is set again.
of
Wake-up (if in Sleep mode)
the
Interrupt to CPU
DS40044G-page 109
status
of
their
(1)
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