ATA6612P-PLQW Atmel, ATA6612P-PLQW Datasheet - Page 211
ATA6612P-PLQW
Manufacturer Part Number
ATA6612P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6612P-PLQW
Manufacturer:
UPI
Quantity:
230
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6.17.8
9111H–AUTO–01/11
Multi-processor Communication Mode
Table 6-73.
The recommendations of the maximum receiver baud rate error was made under the assump-
tion that the Receiver and Transmitter equally divides the maximum total error.
There are two possible sources for the receivers baud rate error. The Receiver’s system clock
(XTAL) will always have some minor instability over the supply voltage range and the temper-
ature range. When using a crystal to generate the system clock, this is rarely a problem, but
for a resonator the system clock may differ more than 2% depending of the resonators toler-
ance. The second source for the error is more controllable. The baud rate generator can not
always do an exact division of the system frequency to get the baud rate wanted. In this case
an UBRRn value that gives an acceptable low error can be used if possible.
Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering
function of incoming frames received by the USART Receiver. Frames that do not contain
address information will be ignored and not put into the receive buffer. This effectively reduces
the number of incoming frames that has to be handled by the CPU, in a system with multiple
MCUs that communicate via the same serial bus. The Transmitter is unaffected by the
MPCMn setting, but has to be used differently when it is a part of a system utilizing the
Multi-processor Communication mode.
If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit
indicates if the frame contains data or address information. If the Receiver is set up for frames
with nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames.
When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address.
When the frame type bit is zero the frame is a data frame.
The Multi-processor Communication mode enables several slave MCUs to receive data from a
master MCU. This is done by first decoding an address frame to find out which MCU has been
addressed. If a particular slave MCU has been addressed, it will receive the following data
frames as normal, while the other slave MCUs will ignore the received frames until another
address frame is received.
# (Data+Parity Bit)
10
D
5
6
7
8
9
Recommended Maximum Receiver Baud Rate Error for Double Speed Mode
(U2Xn = 1)
R
slow
94.12
94.92
95.52
96.00
96.39
96.70
(%)
R
105.66
104.92
104,35
103.90
103.53
103.23
fast
(%)
Atmel ATA6612/ATA6613
Max Total Error (%)
+5.66/-5.88
+4.92/-5.08
+4.35/-4.48
+3.90/-4.00
+3.53/-3.61
+3.23/-3.30
Recommended Max
Receiver Error (%)
±2.5
±2.0
±1.5
±1.5
±1.5
±1.0
211
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