ATA6612P-PLQW Atmel, ATA6612P-PLQW Datasheet - Page 75
ATA6612P-PLQW
Manufacturer Part Number
ATA6612P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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9111H–AUTO–01/11
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be
used to wake the device from sleep-modes, and also as a general system timer. One example
is to limit the maximum time allowed for certain operations, giving an interrupt when the opera-
tion has run longer than expected. In System Reset mode, the WDT gives a reset when the
timer expires. This is typically used to prevent system hang-up in case of runaway code. The
third mode, Interrupt and System Reset mode, combines the other two modes by first giving
an interrupt and then switch to System Reset mode. This mode will for instance allow a safe
shutdown by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to
System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Inter-
rupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security,
alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing
WDE and changing time-out configuration is as follows:
The following code example shows one assembly and one C function for turning off the
Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling inter-
rupts globally) so that no interrupts will occur during the execution of these functions.
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE)
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP)
and WDE. A logic one must be written to WDE regardless of the previous value of the
WDE bit.
as desired, but with the WDCE bit cleared. This must be done in one operation.
Atmel ATA6612/ATA6613
75
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