ATA6612P-PLQW Atmel, ATA6612P-PLQW Datasheet - Page 214
ATA6612P-PLQW
Manufacturer Part Number
ATA6612P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6612P-PLQW
Manufacturer:
UPI
Quantity:
230
- Current page: 214 of 364
- Download datasheet (7Mb)
6.17.9.3
214
Atmel ATA6612/ATA6613
USART Control and Status Register n B – UCSRnB
Initial Value
Read/Write
• Bit 2 – UPEn: USART Parity Error
• Bit 1 – U2Xn: Double the USART Transmission Speed
• Bit 0 – MPCMn: Multi-processor Communication Mode
• Bit 7 – RXCIEn: RX Complete Interrupt Enable n
• Bit 6 – TXCIEn: TX Complete Interrupt Enable n
• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n
• Bit 4 – RXENn: Receiver Enable n
• Bit 3 – TXENn: Transmitter Enable n
This bit is set if the next character in the receive buffer had a Parity Error when received
and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the
receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA.
This bit only has effect for the asynchronous operation. Write this bit to zero when using
synchronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively
doubling the transfer rate for asynchronous communication.
This bit enables the Multi-processor Communication mode. When the MPCMn bit is writ-
ten to one, all the incoming frames received by the USART Receiver that do not contain
address information will be ignored. The Transmitter is unaffected by the MPCMn setting.
For more detailed information see
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete
interrupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag
in SREG is written to one and the RXCn bit in UCSRnA is set.
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag
in SREG is written to one and the TXCn bit in UCSRnA is set.
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty inter-
rupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the UDREn bit in UCSRnA is set.
Writing this bit to one enables the USART Receiver. The Receiver will override normal
port operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive
buffer invalidating the FEn, DORn, and UPEn Flags.
Writing this bit to one enables the USART Transmitter. The Transmitter will override nor-
mal port operation for the TxDn pin when enabled. The disabling of the Transmitter
(writing TXENn to zero) will not become effective until ongoing and pending transmissions
are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not
contain data to be transmitted. When disabled, the Transmitter will no longer override the
TxDn port.
Bit
RXCIEn
R/W
7
0
TXCIEn
R/W
6
0
UDRIEn
R/W
5
0
“Multi-processor Communication Mode” on page
RXENn
R/W
4
0
TXENn
R/W
3
0
UCSZn2
R/W
2
0
RXB8n
R
1
0
TXB8n
R/W
9111H–AUTO–01/11
0
0
UCSRnB
211.
Related parts for ATA6612P-PLQW
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
BOARD DEMO LIN-MCM FOR ATA6612
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
DEV KIT FOR AVR/AVR32
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
AM-FM Receiver IC U4255BM-M
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Monolithic Integrated Feature Phone Circuit
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Multistandard Video-IF and Quasi Parallel Sound Processing
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
High-performance EE PLD
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
8-bit Flash Microcontroller
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
2-Wire Serial EEPROM
Manufacturer:
ATMEL Corporation
Datasheet: