ATTINY26-16PU Atmel, ATTINY26-16PU Datasheet
ATTINY26-16PU
Specifications of ATTINY26-16PU
Related parts for ATTINY26-16PU
ATTINY26-16PU Summary of contents
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... Speed Grades – MHz for ATtiny26L – MHz for ATtiny26 • Power Consumption at 1 MHz, 3V and 25°C for ATtiny26L – Active 16 MHz, 5V and 25°C: Typ 15 mA – Active 1 MHz, 3V and 25°C: 0.70 mA – Idle Mode 1 MHz, 3V and 25°C: 0.18 mA – Power-down Mode: < 1 µA ® ...
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... Pin Configuration Note: ATtiny26(L) 2 (MOSI/DI/SDA/OC1A) PB0 (MISO/DO/OC1A) PB1 (SCK/SCL/OC1B) PB2 (OC1B) PB3 VCC GND (ADC7/XTAL1) PB4 (ADC8/XTAL2) PB5 (ADC9/INT0/T0) PB6 (ADC10/RESET) PB7 MLF Top View NC 1 (OC1B) PB3 VCC 4 GND (ADC7/XTAL1) PB4 7 (ADC8/XTAL2) PB5 8 The bottom pad under the QFN/MLF package should be soldered to ground. ...
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... The ATtiny26(L) provides 2K bytes of Flash, 128 bytes EEPROM, 128 bytes SRAM general purpose I/O lines, 32 general purpose working registers, two 8-bit Timer/Counters, one with PWM outputs, internal and external Oscillators, internal and external interrupts, program- mable Watchdog Timer, 11-channel, 10-bit Analog to Digital Converter with two differential voltage input gain stages, and four software selectable power saving modes ...
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... Block Diagram Figure 1. The ATtiny26(L) Block Diagram VCC GND AVCC ATtiny26(L) 4 8-BIT DATA BUS PROGRAM STACK COUNTER POINTER PROGRAM SRAM FLASH INSTRUCTION GENERAL REGISTER PURPOSE REGISTERS X INSTRUCTION Y DECODER Z CONTROL ALU LINES STATUS REGISTER PROGRAMMING ISP INTERFACE LOGIC DATA REGISTER DATA DIR. ...
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Pin Descriptions VCC Digital supply voltage pin. GND Digital ground pin. AVCC AVCC is the supply voltage pin for Port A and the A/D Converter (ADC). It should be externally connected to V through a low-pass filter. See page 94 ...
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... These code examples assume that the part specific header file is included before compi- lation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling compiler dependent. Please confirm with the C compiler documentation for more details. ATtiny26(L) 6 1477K–AVR–08/10 ...
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... The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 2 shows the ATtiny26(L) AVR Enhanced RISC microcontroller architecture. In addition to the register opera- tion, the conventional memory addressing modes can be used on the Register File as well. This is enabled by the fact that the Register File is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations ...
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... Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. General Purpose Figure 3 shows the structure of the 32 general purpose working registers in the CPU. Register File Figure 3. AVR CPU General Purpose Working Registers ATtiny26( … ...
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All of the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exceptions are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and ...
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... The Zero Flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. ATtiny26( ...
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... Stack Pointer – SP The ATtiny26(L) Stack Pointer is implemented as an 8-bit register in the I/O space location $3D ($5D). As the ATtiny26(L) data memory has 224 ($E0) locations, eight bits are used. Bit $3D ($5D) Read/Write Initial Value The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located ...
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... Operand address is contained in 6 bits of the instruction word the destination or source reg- ister address. Data Direct Figure 8. Direct Data Addressing A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. Data Indirect with Figure 9. Data Indirect with Displacement Displacement ATtiny26( Rr/Rd 16 LSBs 15 ...
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Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction word. Data Indirect Figure 10. Data Indirect Addressing Operand address is the contents of the X-, Y-, or ...
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... Addressing, IJMP and ICALL Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). Relative Program Figure 15. Relative Program Memory Addressing Addressing, RJMP and RCALL ATtiny26(L) 14 PROGRAM MEMORY PROGRAM MEMORY PROGRAM MEMORY +1 $000 $3FF $000 ...
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Program execution continues at address The relative address k is from -2048 to 2047. 1477K–AVR–08/10 15 ...
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... Figure 17. Single Cycle ALU Operation Register Operands Fetch ALU Operation Execute The internal data SRAM access is performed in two System Clock cycles as described in Figure 18. ATtiny26( System Clock Ø 1st Instruction Fetch 2nd Instruction Fetch 3rd Instruction Fetch ...
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... Programmable gram storage. Since all instructions are 16- or 32-bit words, the Flash is organized 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny26(L) Pro- Flash Program gram Counter – PC – bits wide, thus addressing the 1024 program memory addresses, see Memory “ ...
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... See “Program and Data Addressing Modes” on page 11 for a detailed description of the different addressing modes. EEPROM Data The ATtiny26(L) contains 128 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written (see “Memory Programming” on page Memory 107) ...
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... Initial Value • Bit 7..4 – RES: Reserved Bits These bits are reserved bits in the ATtiny26(L) and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. ...
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... Store constants in Flash memory if the ability to change memory contents from software is not required. Flash memory can not be updated by the CPU, and will not be subject to corruption. I/O Memory The I/O space definition of the ATtiny26(L) is shown in Table 2 Table 2. ATtiny26(L) I/O Space Address Hex ...
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... Note: All ATtiny26(L) I/O and peripheral registers are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range $00 - $1F are 1477K– ...
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... SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chap- ter for more details. For compatibility with future devices, reserved bits should be written zero if accessed. Reserved I/O memory addresses should never be written. ATtiny26(L) 22 1477K–AVR–08/10 ...
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System Clock and Clock Options Clock Systems Figure 20 presents the principal clock systems in the AVR and their distribution. All of the clocks and their need not be active at a given time. In order to reduce power consumption, ...
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... Internal PLL for Fast The internal PLL in ATtiny26(L) generates a clock frequency that is 64x multiplied from nomi- Peripheral Clock nally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC Generation – clk Oscillator which is automatically divided down to 1 MHz, if needed. See the Figure 21 on page PCK 24 ...
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Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below on Table 3. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.The ...
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... Figure 22. Crystal Oscillator Connections The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 6. Table 6. Crystal Oscillator Operating Modes CKSEL3..1 (1) 101 110 111 Note: ATtiny26( 5.0V) Typ Time-out ( Frequency ...
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The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 7. Table 7. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 Notes: Low-frequency To use ...
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... The operating mode is selected by the fuses CKSEL3..0 as shown in Table 9. Table 9. External RC Oscillator Operating Modes When this oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 10. Table 10. Start-up Times for the External RC Oscillator Clock Selection SUT1.. Notes: ATtiny26( CKSEL3..0 0101 0110 0111 1000 ...
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... RC Oscillator. At 5V, 25°C and 1.0 MHz Oscillator frequency selected, this calibration gives a fre-quency within ± the nominal frequency. Using run-time calibra- tion methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 1% accuracy at any given V chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the reset time-out. For more information on the pre-programmed calibration value, see the section “ ...
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... When applying an external clock required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behaviour required to ensure that the MCU is kept in reset during such changes in the clock frequency. ATtiny26(L) 30 Min Frequency in Percentage of Nominal Frequency ...
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High Frequency There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as PLL Clock – a system ...
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... Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. Figure 25 shows the reset logic for the ATtiny26(L). Table 16 shows the timing and electrical parameters of the reset circuitry for ATtiny26(L). ...
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... V antees that a Brown-out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL=1 for ATtiny26L and BODLEVEL=0 for ATtiny26. BODLEVEL=1 is not applicable for ATtiny26. decreases below detection level. ...
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... Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V positive edge, the delay timer starts the MCU after the Time-out period t Figure 28. External Reset During Operation TIME-OUT INTERNAL ATtiny26( POT VCC V ...
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... Brown-out ATtiny26(L) has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD Detection is enabled (BODEN programmed), and V Reset is immediately activated. When V Reset is deactivated after a delay. The delay is defined by the user in the same way as the delay of POR signal, in Table 29 ...
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... Read/Write Initial Value • Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny26(L) and always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set (one Watchdog Reset occurs. The bit is reset (zero Power-on Reset writing a logic zero to the flag. • ...
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... SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Table 19 on page 39 presents the different clock systems in the ATtiny26, and their distribution. The figure is helpful in selecting an appropriate sleep mode. MCU Control The MCU Control Register contains control bits for general MCU functions. Register – ...
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... Sources” on page 25. Note that if a level triggered external interrupt or pin change interrupt is used from Power-down mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. ATtiny26(L) 38 (1) ISC00 ...
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If the wake-up condition disappears before the MCU wakes up and starts to execute, e.g., a low level on INT0 is not held long enough, the interrupt causing the wake-up will not be executed. Standby Mode When the SM1..0 bits ...
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... In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to “Digital Input Enable and Sleep Modes” on page 45 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V ATtiny26(L) 40 Parameter Bandgap reference voltage ...
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I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the ...
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... If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11 intermediate step. ATtiny26(L) 42 (1) Pxn PUD: ...
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Table 21 summarizes the control signals for the pin value. Table 21. Port Pin Configurations DDxn Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read ...
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... Figure 34. Synchronization when Reading a Software Assigned Pin Value INSTRUCTIONS ATtiny26(L) 44 SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 0xFF nop in r17, PINx 0x00 0xFF t pd 1477K–AVR–08/10 ...
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The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The ...
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... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 35. Alternate Port Functions Note: ATtiny26( GND is not recommended, since this may cause excessive currents if the pin is CC ...
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Table 22 summarizes the function of the overriding signals. The pin and port indexes from Fig- ure 35 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 22. ...
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... The masking alternate function is the Analog Comparator. Digital input is enabled on pin PA7 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function. • ADC5/AIN0 Port – A, Bit 6 ATtiny26( ...
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AIN0: Analog Comparator Positive input and ADC5: ADC input channel 5 as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator or analog to digital converter. PCINT1: ...
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... Table 25. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Notes: ATtiny26(L) 50 PA3/AREF/PCINT1 ADMUX[REFS0] 0 ADMUX[REFS0 (1) PCINT1_ENABLE • (2) ~ ADMUX[REFS0] 1 PCINT1 ANALOG REFERENCE INPUT 1. Note that the PCINT1 Interrupt is only enabled if both the Global Interrupt Flag is enabled, the PCIE1 flag in GIMSK is set and the alternate function of the pin is disabled as described in “ ...
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Alternate Functions Of Port B has an alternate functions for the ADC, Clocking, Timer/Counters, USI, SPI programming Port B and pin change interrupt. The ADC is described in “Analog to Digital Converter” on page 94, Clocking in “AVR CPU Core” ...
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... OC1B: Output Compare match output: The PB3 pin can serve as an output for the Timer/Counter1 compare match B. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode. ATtiny26(L) 52 1477K–AVR–08/10 ...
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PCINT0: Pin Change Interrupt 0 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate function is the output compare ...
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... Interrupt” on page 62. 5. Not operator is marked with “~”. 6. The operation of the Timer/Counter0 with external clock disabled is described in “8-bit Timer/Counter0” on page 65. 7. External clock is selected by the PLLCK and CKSEL Fuses as described in “Clock Sources” on page 25. ATtiny26(L) 54 PB6/ADC9/INT0/TO/ PB5/ADC8/XTAL2/ ...
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Table 28. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PB3/OC1B/PCINT0 PUOE 0 PUOV 0 DDOE 0 DDOV 0 (1) PVOE OC1B_ENABLE PVOV OC1B DIEOE PCINT0_ENABLE ~OC1B_ENABLE DIEOV 1 DI PCINT0 AIO – Notes: 1. Enabling of the Timer/Counter1 ...
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... Port B Data Register – Bit PORTB $18 ($38) Read/Write Initial Value Port B Data Direction Bit Register – DDRB $17 ($37) Read/Write Initial Value Port B Input Pins Bit Address – PINB $16 ($36) Read/Write Initial Value ATtiny26( PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 R/W R/W R/W R ...
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... Interrupts Interrupt Vectors The ATtiny26(L) provides eleven interrupt sources. These interrupts and the separate Reset Vector, each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the Status Register in order to enable the interrupt ...
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... Initial Value • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny26(L) and always reads as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled ...
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... These bits are reserved bits in the ATtiny26(L) and always read as zero. Timer/Counter Bit Interrupt Mask $39 ($59) Register – TIMSK Read/Write Initial Value • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny26(L) and always reads as zero. 1477K–AVR–08/ – INTF0 PCIF – ...
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... Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter0 occurs. The Overflow Flag (Timer0) is set (one) in the Timer/Counter Interrupt Flag Register – TIFR. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the ATtiny26(L) and always reads as zero. Timer/Counter Bit Interrupt Flag Register $38 ($58) – ...
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... When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the ATtiny26(L) and always reads as zero. 1477K–AVR–08/10 61 ...
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... This implies that one external event might cause several interrupts. The value of the programmed fuse is “0” and unprogrammed is “1”. Each of the lines enables the alternate function so “or” function of the lines enables the function. ATtiny26(L) 62 µs 1477K–AVR–08/10 ...
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Table 30. Alternative Functions Pin PA3 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Notes: A fuse value of “0” is programmed, “1” is unprogrammed. 1477K–AVR–08/10 Control Register[Bit Name] which Alternate Function set the Alternate Function AREF ADMUX[REFS0] ...
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... Timer/Counters The ATtiny26(L) provides two general purpose 8-bit Timer/Counters. The Timer/Counters have separate prescaling selection from the separate prescaler. The Timer/Counter0 clock (CK) as the clock timebase. The Timer/Counter1 has two clocking modes, a synchronous mode and an asynchronous mode. The synchronous mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base ...
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Timer/Counter1 Figure 37 shows the Timer/Counter1 prescaler. For Timer/Counter1 the clock selections are between PCK to PCK/16384 and stop in asynchronous mode and CK to CK/16384 and stop in Prescaler synchronous. The clock options are described in Table 34 on ...
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... Initial Value • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny26(L) and always read as zero. • Bit 3 – PSR0: Prescaler Reset Timer/Counter0 When this bit is set (one), the prescaler of the Timer/Counter0 will be reset. The bit will be cleared by hardware after the operation is performed ...
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The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used, the correspond- ing setup must be performed in the actual Data Direction ...
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... The synchronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of the PCK when the system clock is high. If the frequency of the sys- tem clock is too high risk that data or control values are lost. The following Figure 40 shows the block diagram for Timer/Counter1. ATtiny26(L) 68 8-BIT DATABUS Input syncronization ...
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Figure 40. Timer/Counter1 Block Diagram Three status flags (overflow and compare matches) are found in the Timer/Counter Interrupt Flag Register – TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1A and TCCR1B. The interrupt enable/disable settings are found ...
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... Writing a logical one to this bit forces a change in the Compare Match output pin PB3 (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can ATtiny26( ...
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... When this bit is set (one), the Timer/Counter prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read as zero. • Bit 5..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny26(L) and always read as zero. 1477K–AVR–08/ ...
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... The Timer/Counter Output Compare Register A contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and OCR1A to the same value does not generate a compare match. ATtiny26(L) 72 Description CS12 ...
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... Read/Write Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny26(L) and always read as zero. • Bit 2 – PCKE: PCK Enable The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock mode is enabled and fast 64 MHz PCK clock is used as Timer/Counter1 clock source ...
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... Timer/Counter1 acts as an up-counter, counting from $ the value specified in the Output Compare Register (OCR1C), and starting from $00 up again. A compare match with OC1C will set an Overflow Interrupt Flag (TOV1) after a synchronization delay following the compare event. ATtiny26( non-overlap 1477K–AVR–08/10 ...
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Table 35. Compare Mode Select in PWM Mode COM1x1 Note that in PWM mode, writing to the Output Compare Registers OCR1A or OCR1B, the data value is first transferred to a temporary location. The value is ...
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... Timer Output Compare flags and interrupts. The frequency of the PWM will be Timer Clock 1 Frequency divided by (OCR1C value + 1). See the following equation: Resolution shows how many bit is required to express the value in the OCR1C Register cal- culated by following equation ATtiny26(L) 76 COM1x0 OCR1x Output OC1x ...
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Table 37. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode PWM Frequency (kHz) 1477K–AVR–08/10 Clock Selection CS13..CS10 20 PCK/16 30 PCK/16 40 PCK/8 50 PCK/8 60 PCK/8 70 PCK/4 80 PCK/4 90 PCK/4 100 PCK/4 110 PCK/4 120 PCK/4 130 ...
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... Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATtiny26(L) and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
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The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watch- dog Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in Table 38. Table 38. Watchdog Timer Prescale Select WDP2 0 ...
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... The clock can be selected from three different sources: the SCK pin, Timer 0 overflow, or from software. The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start con- dition is detected, or after the counter overflows. ATtiny26(L) 80 SCKmax ...
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Register Descriptions USI Data Register – Bit USIDR $0F ($2F) Read/Write Initial Value The USI uses no buffering of the serial register, i.e., when accessing the Data Register (USIDR) the serial register is accessed directly serial clock occurs ...
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... Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt when the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed. Refer to the description of “Bit 6 – USIOIF: Counter Overflow Interrupt Flag” on page 81 for fur- ther details. ATtiny26( ...
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Bit 5..4 – USIWM1..0: Wire Mode These bits set the type of wire mode to be used. Basically only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode ...
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... When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ- ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. ATtiny26(L) 84 Shift Register Clock ...
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Functional Descriptions Three-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software if necessary. ...
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... The second and third instructions clears the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle SCK (PORTB2). The loop is repeated 16 times. ATtiny26(L) 86 out ...
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The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/2): SPITransfer_Fast: ret SPI Slave Operation The following code demonstrates how to use the USI module as a SPI slave: Example ...
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... The clock is generated by the master by toggling the PB2 pin via the PORTB Register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI- bus, must be implemented to control the data flow. ATtiny26(L) 88 Bit7 Bit6 Bit5 ...
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Figure 48. Two-wire Mode, Typical Timing Diagram SDA SCL Referring to the timing diagram (Figure 48.), a bus transfer involves the following steps: 1. The a start condition is generated by the master by forcing the SDA low line while ...
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... External Interrupt The overflow flag and interrupt enable bit are then used for the external interrupt. This feature is selected by the USICS1 bit. Software Interrupt The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. ATtiny26(L) 90 1477K–AVR–08/10 ...
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Analog The Analog Comparator compares the input values on the positive pin PA6 (AIN0) and negative pin PA7 (AIN1). When the voltage on the positive pin PA6 (AIN0) is higher than the voltage on Comparator the negative pin PA7 (AIN1), ...
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... Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 41. Table 41. ACIS1/ACIS0 Settings ACIS1 Note: ATtiny26(L) 92 (1) ACIS0 Interrupt Mode 0 Comparator Interrupt on Output Toggle 1 Reserved 0 ...
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Table 42. Analog Comparator Input Selection ACME Notes: 1477K–AVR–08/10 (3) ADEN MUX3...0 Analog Comparator Negative Input X XXXX AIN1 1 XXXX AIN1 ...
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... Sleep Mode Noise Canceler The ATtiny26(L) features a 10-bit successive approximation ADC. The ADC is connected to an 11-channel Analog Multiplexer which allows eight differential voltage input combinations or 11 single-ended voltage inputs constructed from seven pins from Port A and four pins from Port B. ...
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Figure 51. Analog to Digital Converter Block Schematic VCC AREF GND ADC10 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approxi- mation. The ...
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... Conversion Timing The successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz lower resolution than 10 bits is needed, the input clock frequency to the ADC can be as high as 1000 kHz to get a higher sample rate. ATtiny26(L) 96 Reset ADEN 7-BIT ADC PRESCALER ...
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The ADC module contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. The ADPS bits in ADCSR are used to generate a proper ADC clock input frequency from any chip clock frequency above 100 kHz. ...
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... ADC clock cycle before the conversion completes (ADIF in ADCSR is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written. ATtiny26(L) 98 One Conversion 1 ...
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Special care should be taken when changing differential channels. Once a differential channel has been selected, the gain stage may take as much as 125 µs to stabilize to the new value. Thus conversions should not be started within the ...
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... ADMUX = 0xEB (ADC0 - ADC1, 20x gain, 2.56V reference, left adjusted result) Voltage on ADC0 is 400 mV, voltage on ADC1 is 300 mV. ADCR = 1024 * 20 * (400 - 300) / 2560 = 800 = 0x320 ADCL will thus read 0x00, and ADCH will read 0xC8. Writing zero to ADLAR right adjusts the result: ADCL = 0x20, ADCH = 0x03. ATtiny26(L) 100 Output Code 0x3FF 0x000 ...
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ADC Multiplexer Bit Selection Register – $07 ($27) ADMUX Read/Write Initial Value • Bit 7, 6 – REFS1, REFS0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 45. If these bits are ...
Page 102
... Note: ATtiny26(L) 102 Single Ended Positive Differential Input Input ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC0 ADC0 N/A ADC1 ...
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ADC Control and Bit Status Register – $06 ($26) ADCSR Read/Write Initial Value • Bit 7 – ADEN: ADC Enable Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is turned ...
Page 104
... These bits represent the result from the conversion. For differential channels, this is the absolute value after gain adjustment, as indicated in Table 46 on page 102. For single ended channels, $000 represents analog ground, and $3FF represents the selected reference voltage minus one LSB. ATtiny26(L) 104 ADPS1 0 ...
Page 105
... If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: Techniques 1. The analog part of the ATtiny26(L) and all analog components in the application should have a separate analog ground plane on the PCB. This ground plane is connected to the digital ground plane via a single point on the PCB. ...
Page 106
... Figure 57. ADC Power Connections ATtiny26(L) 106 (MOSI/DI/SDA/OC1A) PB0 1 (MISO/DO/OC1A) PB1 2 (SCK/SCL/OC1B) PB2 3 (OC1B) PB3 4 VCC 5 GND 6 (ADC7/XTAL1) PB4 7 8 (ADC8/XTAL2) PB5 (ADC9/INT0/T0) PB6 9 10 (ADC10/RESET) PB7 PA0 (ADC0 PA1 (ADC1) PA2 (ADC2) 18 PA3 (AREF) 17 GND 16 AVCC 15 14 PA4 (ADC3) PA5 (ADC4) ...
Page 107
... Memory Programming Program and Data The ATtiny26 provides two Lock bits which can be left unprogrammed (“1”) or can be pro- grammed (“0”) to obtain the additional features listed in Table 49. The Lock bits can only be Memory Lock Bits erased to “1” with the Chip Erase command. ...
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... Fuse Bits The ATtiny26 has two Fuse bytes. Table 50 and Table 51 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 50. Fuse High Byte ...
Page 109
... Table 53. No. of Words in a Page and no. of Pages in the EEPROM EEPROM Size 128 bytes Parallel This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATtiny26. Pulses are assumed Programming least 250 ns unless otherwise noted. Parameters, Pin Mapping, and ...
Page 110
... Table 54. Pin Name Mapping Signal Name in Programming Mode WR XA0 XA1/BS2 PAGEL/BS1 OE RDY/BSY DATA Note: Table 55. Pin Values used to Enter Programming Mode Pin PAGEL/BS1 XA1/BS2 XA0 WR ATtiny26(L) 110 WR PB0 XA0 PB1 XA1/BS2 PB2 PAGEL/BS1 PB3 PB5 OE PB6 RDY/BSY +12 V RESET XTAL1/PB4 GND ...
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Table 56. XA1 and XA0 Coding XA1 Note: Table 57. Command Byte Bit Coding Command Byte 1477K–AVR–08/10 (1) XA0 Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by ...
Page 112
... Skip writing the data value $FF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase. • Address high byte needs only be loaded before programming or reading a new 256-word window in Flash or 256-byte EEPROM. This consideration also applies to Signature bytes reading. ATtiny26(L) 112 1477K–AVR–08/10 ...
Page 113
Chip Erase The Chip Erase will erase the Flash and EEPROM not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. ...
Page 114
... Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 59. Addressing the Flash which is Organized in Pages Note: ATtiny26(L) 114 PCMSB PROGRAM PCPAGE COUNTER ...
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Figure 60. Programming the Flash Waveforms PAGEL/BS1 RESET +12V Note: Programming the The EEPROM is organized in pages, see Table 53 on page 109. When programming the EEPROM EEPROM, the program data is latched into a page buffer. This allows ...
Page 116
... Command and Data loading Load Command “0100 0000” Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 and BS2 to “0”. 4. Give WR a negative pulse and wait for RDY/BSY to go high. ATtiny26(L) 116 $11 ADDR ...
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Programming the The algorithm for programming the Fuse high bits is as follows (refer to “Programming the Flash” Fuse High Bits on page 113 for details on Command and Data loading Load Command “0100 0000” Load ...
Page 118
... Set OE to “0” and BS1 to “1”. The Calibration byte can now be read at DATA. 4. Set OE to “1”. Parallel Programming Figure 64. Parallel Programming Timing, Including some General Timing Requirements Characteristics (DATA, XA0, XA1/BS2 ATtiny26(L) 118 Fuse Low Byte 0 Lock Bits Fuse High Byte ...
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Figure 65. Parallel Programming Timing, Loading Sequence with Timing Requirements PAGEL/BS1 Note: Figure 66. Parallel Programming Timing, Reading Sequence (Within the Same Page) with Tim- ing Requirements PAGEL/BS1 XA1/BS2 Note: 1477K–AVR–08/10 LOAD ADDRESS (LOW BYTE) t XLXH XTAL1 DATA ADDR0 ...
Page 120
... WLRH_CE t XLOL t BVDV t OLDV t OHDZ Notes: ATtiny26(L) 120 Parameter Programming Enable Voltage Programming Enable Current Data and Control Valid before XTAL1 High XTAL1 Low to XTAL1 High XTAL1 Pulse Width High Data and Control Hold after XTAL1 Low XTAL1 Low to WR Low ...
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Serial Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- Downloading put). After RESET is set ...
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... SPI Serial When writing serial data to the ATtiny26, data is clocked on the rising edge of SCK. Programming When reading data from the ATtiny26, data is clocked on the falling edge of SCK. See Figure Algorithm 68, Figure 69, and Table 69 for timing details. To program and verify the ATtiny26 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 61): 1 ...
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Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value $FF. At the time the device is ready for a new page, the programmed value ...
Page 124
... Read Calibration Byte 0011 1000 Note address high bits b = address low bits – Low byte, 1 – High Byte o = data out i = data don’t care ATtiny26(L) 124 Instruction Format Byte 2 Byte 3 Byte4 0101 0011 xxxx xxxx xxxx xxxx 100x xxxx ...
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Serial Programming Figure 69. Serial Programming Timing Characteristics Table 62. Serial Programming Characteristics, T Otherwise Noted) Symbol 1/t CLCL t CLCL 1/t CLCL t CLCL t SHSL t SLSH t OVSH t SHOX t SLIV Note: 1477K–AVR–08/10 MOSI t OVSH ...
Page 126
... Input Leakage I IL Current I/O Pin Input Leakage I IH Current I/O Pin R Reset Pull-up Resistor RST R I/O Pin Pull-up Resistor pu ATtiny26(L) 126 *NOTICE: + 0.5V CC Condition Min. Except XTAL1 pin and -0.5 RESET pins Except XTAL1 and 0.6V CC RESET pins XTAL1 pin, External -0 ...
Page 127
... If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 6. Minimum V for Power-down is 2.5V. CC 1477K–AVR–08/10 Condition Min. Active 1 MHz (ATtiny26L) Active 4 MHz (ATtiny26L) Active 8 MHz (ATtiny26) Idle 1 MHz (ATtiny26L) Idle 4 MHz (ATtiny26L) Idle 8 MHz (ATtiny26) WDT enabled WDT disabled - ...
Page 128
... CLCL t CLCL t CHCX t CLCX t CLCH t CHCL Δ t CLCL Table 64. External RC Oscillator, Typical Frequencies Notes: ATtiny26(L) 128 V IH1 V IL1 Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Change in period from one clock cycle to the next (1) R [kΩ] ...
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ADC Characteristics Table 65. ADC Characteristics, Single Ended Channels, T Symbol Parameter Resolution Absolute Accuracy (Including INL, DNL, Quantization Error, Gain and Offset Error) Integral Non-Linearity (INL) Differential Non-Linearity (DNL) Gain Error Offset error Clock Frequency Conversion Time AVCC Analog ...
Page 130
... ADC Conversion Output Input Bandwidth V Internal Voltage Reference INT R Reference Input Resistance REF R Analog Input Resistance AIN Notes: 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 5.5V. ATtiny26(L) 130 = -40°C to +85°C A Condition Min Gain = 1x Gain = 20x Gain = 4V REF CC ADC clock = 50 - 200 kHz ...
Page 131
... ATtiny26 The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and Typical with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock Characteristics source ...
Page 132
... Figure 72. Active Supply Current vs. Frequency ( MHz) Figure 73. Active Supply Current vs. V ATtiny26(L) 132 ACTIVE SUPPLY CURRENT vs. FREQUENCY MHz 2. Frequency (MHz) (Internal RC Oscillator, 8 MHz) CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 2.5 3 3.5 V 4.0V 3.3V 3. 4.5 5 5.5 (V) CC 5.5V 5.0V 4.5V -40 °C 25 ° ...
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Figure 74. Active Supply Current vs. V Figure 75. Active Supply Current vs. V 1477K–AVR–08/10 CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4 MHz 2.5 3 3.5 CC ...
Page 134
... Figure 76. Active Supply Current vs. V 1.8 1.6 1.4 1.2 0.8 0.6 0.4 0.2 Figure 77. Active Supply Current vs. V ATtiny26(L) 134 (Internal RC Oscillator, 1 MHz) CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 2.5 3 3.5 V (PLL Oscillator) CC ACTIVE SUPPLY CURRENT vs. V PLL OSCILLATOR 25 20 ...
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Figure 78. Active Supply Current vs. V Idle Supply Current Figure 79. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) 1477K–AVR–08/10 CC ACTIVE SUPPLY CURRENT vs. V 32kHz EXTERNAL OSCILLATOR 1.5 ...
Page 136
... Figure 80. Idle Supply Current vs. Frequency ( MHz) Figure 81. Idle Supply Current vs. V ATtiny26(L) 136 IDLE SUPPLY CURRENT vs. FREQUENCY MHz 2. Frequency (MHz) (Internal RC Oscillator, 8 MHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 2 4.0V 3.3V 3. -40 °C 4 4.5 5 5.5 (V) 5.5V 5.0V 4.5V 25 ° ...
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Figure 82. Idle Supply Current vs. V Figure 83. Idle Supply Current vs. V 1477K–AVR–08/10 (Internal RC Oscillator, 4 MHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4 MHz 3.5 3 2.5 2 1 ...
Page 138
... Figure 84. Idle Supply Current vs. V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 Figure 85. Idle Supply Current vs. V ATtiny26(L) 138 (Internal RC Oscillator, 1 MHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 0 2 2.5 3 3.5 V (PLL Oscillator) CC IDLE SUPPLY CURRENT vs. V PLL OSCILLATOR ...
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Figure 86. Idle Supply Current vs. V Power-down Supply Figure 87. Power-down Supply Current vs. V Current 1477K–AVR–08/10 (32 kHz External Oscillator) CC IDLE SUPPLY CURRENT vs. V 32kHz EXTERNAL OSCILLATOR 2.5 ...
Page 140
... Figure 88. Power-down Supply Current vs. V Standby Supply Figure 89. Standby Supply Current vs. V Current ATtiny26(L) 140 POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 2 STANDBY SUPPLY CURRENT vs. V 455 kHz RESONATOR, WATCHDOG TIMER DISABLED 2.5 3 3.5 V (Watchdog Timer Enabled 4.5 5 5.5 ...
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Figure 90. Standby Supply Current vs. V Figure 91. Standby Supply Current vs. V 1477K–AVR–08/10 CC STANDBY SUPPLY CURRENT vs MHz RESONATOR, WATCHDOG TIMER DISABLED 2 ...
Page 142
... Figure 92. Standby Supply Current vs. V Figure 93. Standby Supply Current vs. V 120 100 ATtiny26(L) 142 CC STANDBY SUPPLY CURRENT vs MHz XTAL, WATCHDOG TIMER DISABLED 2 STANDBY SUPPLY CURRENT vs MHz RESONATOR, WATCHDOG TIMER DISABLED 2 MHz XTAL, Watchdog Timer Disabled 4.5 5 5.5 ...
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Figure 94. Standby Supply Current vs. V Figure 95. Standby Supply Current vs. V 1477K–AVR–08/10 STANDBY SUPPLY CURRENT vs MHz XTAL, WATCHDOG TIMER DISABLED 120 100 2.5 3 3.5 STANDBY SUPPLY CURRENT ...
Page 144
... Pin Pull-up Figure 97. I/O Pin Pull-up Resistor Current vs. Input Voltage (V 160 85 °C 140 120 100 ATtiny26(L) 144 CC STANDBY SUPPLY CURRENT vs MHz XTAL, WATCHDOG TIMER DISABLED 2.5 3 3.5 V I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 25 °C -40 ° ...
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Figure 98. I/O Pin Pull-up Resistor Current vs. Input Voltage (V 85 °C Figure 99. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V -40 °C 1477K–AVR–08/10 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 80 25 °C 70 -40 ...
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... Figure 100. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V -40 °C Pin Driver Strength Figure 101. I/O Pin Source Current vs. Output Voltage (V ATtiny26(L) 146 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2. ° ° 0 RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ...
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Figure 102. I/O Pin Source Current vs. Output Voltage (V Figure 103. I/O Pin Sink Current vs. Output Voltage (V 1477K–AVR–08/10 I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 30 -40 ° °C 85 °C 20 ...
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... Figure 104. I/O Pin Sink Current vs. Output Voltage (V Figure 105. Reset Pin as I/O – Source Current vs. Output Voltage (V 1.4 1.2 0.8 0.6 0.4 0.2 ATtiny26(L) 148 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2. 0 RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V -40 ° ...
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Figure 106. Reset Pin as I/O – Source Current vs. Output Voltage (V Figure 107. Reset Pin as I/O –Sink Current vs. Output Voltage (V 1477K–AVR–08/10 RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE 2.5 -40 °C 2 ...
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... Figure 108. Reset Pin as I/O – Sink Current vs. Output Voltage (V Pin Thresholds and Figure 109. I/O Pin Input Threshold Voltage vs. V Hysteresis ATtiny26(L) 150 RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 4.5 4 3.5 3 2.5 2 1 I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' 2 ...
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Figure 110. I/O Pin Input Threshold Voltage vs. V Figure 111. I/O Pin Input Hysteresis vs. V 1477K–AVR–08/10 I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' 2 1 2.5 3 3.5 ...
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... Reset Pin Read as “1”) IH 2.5 1.5 0.5 Figure 113. Reset Pin as I/O – Input Threshold Voltage vs Reset Pin Read as “0”) IL 2.5 1.5 0.5 ATtiny26(L) 152 RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. V VIH, RESET PIN READ AS ' 2 RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. V ...
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Figure 114. Reset Pin as I/O – Pin Hysteresis vs. V Figure 115. Reset Input Threshold Voltage vs. V 1477K–AVR–08/10 RESET PIN AS I/O - PIN HYSTERESIS vs. V 0.7 0.6 0.5 0.4 0.3 0.2 0 2.5 3 ...
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... Figure 116. Reset Input Threshold Voltage vs. V 2.5 1.5 0.5 Figure 117. Reset Input Pin Hysteresis vs. V 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 ATtiny26(L) 154 RESET INPUT THRESHOLD VOLTAGE vs. V VIL, RESET PIN READ AS ' °C 25 °C 1 -40 ° 2 RESET INPUT PIN HYSTERESIS vs ...
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BOD Thresholds and Figure 118. BOD Thresholds vs. Temperature (BOD Level is 4.0V) Analog Comparator Offset Figure 119. BOD Thresholds vs. Temperature (BOD Level is 2.7V) 1477K–AVR–08/10 BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.0V 4.3 4.2 4.1 4 3.9 3.8 ...
Page 156
... Figure 121. Analog Comparator Offset Voltage vs. Common Mode Voltage (V 0.009 0.008 0.007 0.006 0.005 0.004 0.003 0.002 0.001 ATtiny26(L) 156 CC BANDGAP vs. V 2.5 3 3.5 Vcc (V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = Common Mode Voltage (V) ...
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Figure 122. Analog Comparator Offset Voltage vs. Common Mode Voltage (V 0.009 0.008 0.007 0.006 0.005 0.004 0.003 0.002 0.001 Internal Oscillator Figure 123. Watchdog Oscillator Frequency vs. V Speed 1477K–AVR–08/10 ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0 ...
Page 158
... Figure 124. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature 8.9 8.4 7.9 7.4 6.9 6.4 Figure 125. Calibrated 8 MHz RC Oscillator Frequency vs. V 8.5 7.5 6.5 ATtiny26(L) 158 CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE -60 -40 - CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs 2 5.0V 3.5V 2. 100 (˚C) ...
Page 159
Figure 126. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value Figure 127. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature 1477K–AVR–08/10 CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 17.5 15.5 13.5 11.5 9.5 7.5 5.5 3 ...
Page 160
... Figure 129. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value 9.6 8.6 7.6 6.6 5.6 4.6 3.6 2.6 1.6 ATtiny26(L) 160 CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs 2 CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 112 ...
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Figure 130. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature Figure 131. Calibrated 2 MHz RC Oscillator Frequency vs. V 1477K–AVR–08/10 CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 2.15 2.1 2.05 2 1.95 1.9 1.85 1.8 1.75 -60 -40 -20 ...
Page 162
... Figure 132. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 Figure 133. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature 1.04 1.02 0.98 0.96 0.94 0.92 ATtiny26(L) 162 CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 112 OSCCAL VALUE CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1 0.9 -60 ...
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Figure 134. Calibrated 1 MHz RC Oscillator Frequency vs. V Figure 135. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value 1477K–AVR–08/10 CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. V 1.1 1.05 1 0.95 0.9 0.85 2 2.5 3 3.5 CALIBRATED ...
Page 164
... Current Consumption Figure 136. Brown-out Detector Current vs Peripheral Units 0.035 0.03 0.025 0.02 0.015 0.01 0.005 Figure 137. ADC Current vs. V 250 200 150 100 ATtiny26(L) 164 BROWNOUT DETECTOR CURRENT vs. V -40 °C 25 °C 85 ° 2.5 3 3.5 V (AREF = AV CC ADC CURRENT vs. V AREF = AVCC ...
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Figure 138. AREF External Reference Current vs. V Figure 139. Analog Comparator Current vs. V 1477K–AVR–08/10 AREF EXTERNAL REFERENCE CURRENT vs. VCC 250 200 150 100 2.5 3 3.5 ANALOG COMPARATOR CURRENT vs. V 120 100 80 ...
Page 166
... Figure 140. Programming Current vs. V Current Consumption Figure 141. Reset Supply Current vs Reset and Reset (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) Pulsewidth ATtiny26(L) 166 CC PROGRAMMING CURRENT vs. VCC 2 RESET SUPPLY CURRENT vs. V 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 3 ...
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Figure 142. Reset Supply Current vs MHz, Excluding Current Through The Reset Pull-up) Figure 143. Reset Pulsewidth vs. V 1200 1000 1477K–AVR–08/10 CC RESET SUPPLY CURRENT vs MHz, EXCLUDING CURRENT THROUGH THE ...
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... Reserved $0A ($2A) Reserved $09 ($29) Reserved $08 ($28) ACSR ACD $07 ($27) ADMUX REFS1 $06 ($26) ADCSR ADEN $05 ($25) ADCH $04 ($24) ADCL … Reserved $00 ($20) Reserved ATtiny26(L) 168 Bit 6 Bit 5 Bit 4 Bit SP6 SP5 SP4 SP3 INT0 PCIE1 PCIE0 - INTF0 PCIF - - OCIE1A OCIE1B ...
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Instruction Set Summary Mnemonic Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers ADIW Rdl, K Add Immediate to Word SUB Rd, Rr Subtract Two Registers SUBI Rd, K ...
Page 170
... Set T in SREG CLT Clear T in SREG SEH Set Half-carry Flag in SREG CLH Clear Half-carry Flag in SREG NOP No Operation SLEEP Sleep WDR Watchdog Reset ATtiny26(L) 170 Operation Flags Rd ← (Y) None Rd ← (Y), Y ← None Y ← ← (Y) None Rd ← None Rd ← (Z) None Rd ← ...
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... Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 1477K–AVR–08/10 Ordering Code (2) Package ATtiny26L-8PU 20P3 ATtiny26L-8SU 20S ATtiny26L-8SUR 20S ATtiny26L-8MU 32M1-A ATtiny26L-8MUR 32M1-A ATtiny26-16PU 20P3 ATtiny26-16SU 20S ATtiny26-16SUR 20S ATtiny26-16MU 32M1-A ATtiny26-16MUR 32M1-A Package Type (2) Operational Range Industrial (1) (-40° ...
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... A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R ATtiny26(L) 172 D PIN TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual ...
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20S 1477K–AVR–08/10 173 ...
Page 174
... Pin TOP VIEW Pin #1 Notch (0. BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 2325 Orchard Parkway San Jose, CA 95131 R ATtiny26(L) 174 TITLE 32M1-A, 32-pad 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) SIDE VIEW ...
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... Errata The revision letter refers to the revision of the device. ATtiny26 Rev. • First Analog Comparator conversion may be delayed B/C/D 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. ...
Page 176
... Rearranged some sections in the datasheet. Rev. 1477E-10/03 1. Removed Preliminary references. 2. Updated “Features” on page 1. 3. Removed SSOP package reference from “Pin Configuration” on page 2. 4. Updated V 5. Updated “Calibrated Internal RC Oscillator” on page 29. ATtiny26(L) 176 and t in Table 16 on page 33. RST RST 1477K–AVR–08/10 ...
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... Added WD_FUSE period in Table 60 on page 123. 12. Updated “ADC Characteristics” on page 129 and added Table 66, “ADC Characteris- tics, Differential Channels, T 13. Updated “ATtiny26 Typical Characteristics” on page 131. 14. Added LPM Rd, Z and LPM Rd “Instruction Set Summary” on page 169. Rev. 1477C-09/02 1 ...
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... ATtiny26(L) 178 1477K–AVR–08/10 ...
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Table of Features................................................................................................ 1 Contents Pin Configuration ................................................................................ 2 Description........................................................................................... 3 Block Diagram ...................................................................................................... 4 Pin Descriptions.................................................................................................... 5 General Information ............................................................................ 6 Resources ............................................................................................................ 6 Code Examples .................................................................................................... 6 AVR CPU Core ..................................................................................... 7 Architectural Overview.......................................................................................... 7 General Purpose Register ...
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... Alternative USI Usage ........................................................................................ 90 Analog Comparator ........................................................................... 91 Analog to Digital Converter .............................................................. 94 Features ............................................................................................................. 94 Operation ............................................................................................................ 95 Prescaling and Conversion Timing ..................................................................... 96 Changing Channel or Reference Selection ........................................................ 98 ADC Noise Canceler Function............................................................................ 99 ADC Conversion Result...................................................................................... 99 Scanning Multiple Channels ............................................................................. 105 ADC Noise Canceling Techniques ................................................................... 105 Offset Compensation Schemes ........................................................................ 105 ATtiny26(L) ii 1477K–AVR–08/10 ...
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... Instruction Set Summary ................................................................ 169 Ordering Information....................................................................... 171 Packaging Information.................................................................... 172 20P3 ................................................................................................................. 172 20S ................................................................................................................... 173 32M1-A ............................................................................................................. 174 Errata ................................................................................................ 175 ATtiny26 Rev. B/C/D ........................................................................................ 175 Datasheet Revision History ............................................................ 176 Rev. 1477K-08/10............................................................................................. 176 Rev. 1477J-06/07 ............................................................................................. 176 Rev. 1477I-05/06 .............................................................................................. 176 Rev. 1477H-04/06 ............................................................................................ 176 Rev. 1477G-03/05 ............................................................................................ 176 Rev ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...