ATTINY26-16PU Atmel, ATTINY26-16PU Datasheet - Page 31

• Manufacturer Part Number: ATTINY26-16PU
• Description: IC AVR MCU 2K 16MHZ IND 20-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY26-16PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: 2-Wire/ISP/SM-Bus/SPI/UART/USI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 20PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 16 MHz
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Frequency
PLL Clock –
PLL
1477K–AVR–08/10
CLK
There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator
for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as
a system clock source, by programming (“0”) the fuse PLLCK, it is divided by four. When this
option is used, the CKSEL3..0 must be set to “0001”. This clocking option can be used only
when operating between 4.5 - 5.5V to guaratee safe operation. The system clock frequency will
be 16 MHz (64 MHz/4). When using this clock option, start-up times are determined by the SUT
Fuses as shown in Table 15. See also “PCK Clocking System” on page 24.
Table 15. Start-up Times for the PLLCK
SUT1..0
00
01
10
11
Start-up Time from
Power-down
16K CK
1K CK
1K CK
1K CK
Additional Delay from
Reset (V
4.1 ms
65 ms
CC
–
–
= 5.0V)
Recommended Usage
BOD enabled
Fast rising power
Slowly rising power
Slowly rising power
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