ATMEGA8A-AU Atmel, ATMEGA8A-AU Datasheet - Page 64
ATMEGA8A-AU
Manufacturer Part Number
ATMEGA8A-AU
Description
MCU AVR 8K FLASH 16MHZ 32-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8A-AU
Manufacturer:
NXP
Quantity:
1 001
Company:
Part Number:
ATMEGA8A-AU
Manufacturer:
ATM
Quantity:
10 000
Part Number:
ATMEGA8A-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
8159D–AVR–02/11
• RXD – Port D, Bit 0
RXD, Receive Data (Data input pin for the USART). When the USART Receiver is enabled this
pin is configured as an input regardless of the value of DDD0. When the USART forces this pin
to be an input, the pull-up can still be controlled by the PORTD0 bit.
Table 12-9
shown in
Table 12-9.
Table 12-10. Overriding Signals for Alternate Functions in PD3:PD0
Signal Name
PUOE
PUO
OOE
OO
PVOE
PVO
DIEOE
DIEO
DI
AIO
Signal Name
PUOE
PUO
OOE
OO
PVOE
PVO
DIEOE
DIEO
DI
AIO
Figure 12-5 on page
and
Overriding Signals for Alternate Functions PD7:PD4
Table 12-10
PD7/AIN1
0
0
0
0
0
0
0
0
–
AIN1 INPUT
PD3/INT1
INT1 ENABLE
0
0
0
0
0
0
1
INT1 INPUT
–
relate the alternate functions of Port D to the overriding signals
56.
PD6/AIN0
0
0
0
0
0
0
0
0
–
AIN0 INPUT
PD2/INT0
0
0
0
0
0
0
INT0 ENABLE
1
INT0 INPUT
–
PD5/T1
0
0
0
0
0
0
0
0
T1 INPUT
–
PD1/TXD
TXEN
0
TXEN
1
TXEN
TXD
0
0
–
–
PD4/XCK/T0
0
0
0
0
UMSEL
XCK OUTPUT
0
0
XCK INPUT / T0 INPUT
–
ATmega8A
PD0/RXD
RXEN
PORTD0 • PUD
RXEN
0
0
0
0
0
RXD
–
64