ATMEGA8A-PU Atmel, ATMEGA8A-PU Datasheet - Page 33
![MCU AVR 8K FLASH 16MHZ 28-PDIP](/photos/7/21/72189/453-28-dip_sml.jpg)
ATMEGA8A-PU
Manufacturer Part Number
ATMEGA8A-PU
Description
MCU AVR 8K FLASH 16MHZ 28-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8A-PU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
28PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA8A-PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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9.2
9.3
9.4
9.5
8159D–AVR–02/11
Idle Mode
ADC Noise Reduction Mode
Power-down Mode
Power-save Mode
When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Inter-
face, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep
mode basically halts clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the
Two-wire Serial Interface address watch, Timer/Counter2 and the Watchdog to continue
operating (if enabled). This sleep mode basically halts clk
the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, a Two-wire Serial Interface address match interrupt, a Timer/Counter2 interrupt, an
SPM/EEPROM ready interrupt, or an external level interrupt on INT0 or INT1, can wake up the
MCU from ADC Noise Reduction mode.
When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the External Oscillator is stopped, while the external interrupts, the
Two-wire Serial Interface address watch, and the Watchdog continue operating (if enabled).
Only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface
address match interrupt, or an external level interrupt on INT0 or INT1, can wake up the MCU.
This sleep mode basically halts all generated clocks, allowing operation of asynchronous mod-
ules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the
Reset Time-out period, as described in
When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-
save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter2 is clocked asynchronously, i.e. the AS2 bit in ASSR is set,
Timer/Counter2 will run during sleep. The device can wake up from either Timer Overflow or
CPU
and clk
FLASH
“Clock Sources” on page
, while allowing the other clocks to run.
I/O
, clk
CPU
“External Interrupts” on page 67
25.
, and clk
ATmega8A
FLASH
, while allowing
33
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