AT91SAM7S32B-AU-999 Atmel, AT91SAM7S32B-AU-999 Datasheet - Page 660
AT91SAM7S32B-AU-999
Manufacturer Part Number
AT91SAM7S32B-AU-999
Description
IC MCU ARM7 32KB FLASH 48LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7S16-MU.pdf
(779 pages)
Specifications of AT91SAM7S32B-AU-999
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, JTAG, SPI, USART
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
21
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
Minimum Operating Temperature
- 40 C
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 660 of 779
- Download datasheet (11Mb)
40.11.4.3
40.11.5
40.11.5.1
40.11.5.2
660
AT91SAM7S Series Preliminary
Power Management Controller (PMC)
PIO: Drive Low NRST, PA0-PA16 and PA21-PA31
PMC: Slow Clock Selected in PMC and a Transition Occurs on PA1
PMC: Programming CSS in PMC_MCKR Register
It is recommended to use an external pull-up if needed.
When NRST or PA0-PA16 and or PA21-PA31 are set as digital inputs with pull-up enabled, driv-
ing the I/O with an output impedance higher than 500 ohms may not drive the I/O to a logical
zero.
Output impedance must be lower than 500 ohms.
Under certain rare circumstances, when CSS = 00 in PMC_MCKR, and PA1 is set as an input
and a transition occurs on PA1, device malfunction might occur.
Do not transition PA1 as an input when CSS = 00 in PMC_MCKR.
Under certain rare circumstances, reprogramming the CSS value in the PMC_MCKR register
(i.e switching the main clock source) might generate malfunction of the device if the following
two actions occur simultaneously.
Note:
When changing CSS in the PMC_MCKR to switch from
Ensure that the processor is executing out of SRAM and ensure no transition occurs on PA1,
either as an input or output, starting from writing to the PMC_MCKR register until MCKRDY = 1.
1. Switching from:
2. Program code is being executed out of flash, or a transition is occurring on PA1, either
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
And
Problem Fix/Workaround
– PLL Clock to Slow Clock or
– PLL Clock to Main Clock or
– Main Clock to PLL Clock or
– Main Clock to Slow Clock
as an input or output.
– PLL Clock to Slow Clock or
– PLL Clock to Main Clock or
– Main Clock to PLL Clock or
– Main Clock to Slow Clock
This issue does not occur when transitioning from slow clock to main clock or from slow clock to
PLL clock.
6175K–ATARM–30-Aug-10
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