AT89LP6440-20PU Atmel, AT89LP6440-20PU Datasheet - Page 158
AT89LP6440-20PU
Manufacturer Part Number
AT89LP6440-20PU
Description
MCU 8051 64K FLASH ISP 40PDIP
Manufacturer
Atmel
Series
89LPr
Datasheet
1.AT89LP6440-20MU.pdf
(194 pages)
Specifications of AT89LP6440-20PU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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AT89LP6440 - Preliminary
Figure 25-1. In-System Programming Device Connections
The Parallel interface is a special mode of the serial interface, i.e. the serial interface is used to
enable the parallel interface. After enabling the interface serially over P1.7/SCK and P1.5/MOSI,
P1.5 is reconfigured as an active-low output enable (OE) for data on Port 0. When OE = 1, com-
mand, address and write data bytes are input on Port 0 and sampled at the rising edge of SCK.
When OE = 0, read data bytes are output on Port 0 and should be sampled on the falling edge of
SCK. The P1.7/SCK, P1.4/SS and P4.2/RST pins continue to function in the same manner. With
the addition of VDD and GND, the parallel interface requires a minimum of fourteen connections
as shown in
allel interface.
Figure 25-2. Parallel Programming Device Connections
The Programming Interface is the only means of externally programming the AT89LP6440
microcontroller. The Interface can be used to program the device both in-system and in a stand-
alone serial programmer. The Interface does not require any clock other than SCK and is not
limited by the system clock frequency. During Programming the system clock source of the tar-
get device can operate normally.
When designing a system where In-System Programming will be used, the following observa-
tions must be considered for correct operation:
Serial Clock
Figure
Serial Out
Serial In
Clock
25-2. Note that a connection to P1.6/MISO is not required for using the par-
RST
OE
SS
SS
P1.7/SCK
P1.6/MISO
P1.5/MOSI
P1.4/SS
GND
P1.7/SCK
P4.2/RST
P1.5/MOSI
P1.4/SS
GND
AT89LP6440
AT89LP6440
P4.2/RST
P0.7-0
VDD
VDD
8
RST
Data In/Out
3706A–MICRO–9/09
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