PIC16C642-04/SO Microchip Technology, PIC16C642-04/SO Datasheet - Page 66

• Manufacturer Part Number: PIC16C642-04/SO
• Description: IC MCU OTP 4KX14 COMP 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C642-04/SO

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, WDT
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 22
• Ram Memory Size: 176Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 176 B
• Interface Type: RS- 232
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC16C64X & PIC16C66X
9.5
The PIC16C641 and PIC16C642 have four sources of
interrupt, while the PIC16C661 and PIC16C662 have
five sources:
• External interrupt RB0/INT
• TMR0 overflow interrupt
• PORTB change interrupts (pins RB7:RB4)
• Comparator interrupt
• Parallel Slave Port interrupt (PIC16C661/662)
The interrupt control register, (INTCON), records
individual core interrupt requests in flag bits. It also has
various individual enable bits and the global interrupt
enable bit.
The global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on reset.
The “return from interrupt” instruction,
the interrupt routine as well as sets the GIE bit, which
allows any pending interrupt to execute.
Those interrupts associated with the “core” have their
flag and enable bits in the INTCON register. The core
interrupts are: RB0/INT pin interrupt, the RB port
change interrupt, and the TMR0 overflow interrupt. The
INTCON register also contains the Peripheral Interrupt
Enable bit, PEIE. Bit PEIE will enable/mask the periph-
eral interrupts (CM and PSP) from vectoring when bit
PEIE is set/cleared.
Flag bits PSPIF and CMIF are contained in special
function register PIR1. The corresponding interrupt
enable bits (PSPIE and CMIE) are contained in special
function register PIE1.
FIGURE 9-15: INTERRUPT LOGIC
DS30559A-page 66
PSPIE
PSPIF
CMIE
CMIF
Note 1: The Parallel Slave Port is implemented on the PIC16C661 and PIC16C662 only.
Interrupts
(1)
(1)
RBIE
INTE
RBIF
INTF
T0IE
T0IF
PEIE
RETFIE
, exits
Preliminary
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid recur-
sive interrupts.
For external interrupt events, such as the RB0/INT or
Port RB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 9-16).
The latency is the same for one or two cycle
instructions. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests. Individual interrupt
flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
Note 1: Individual interrupt flag bits are set regard-
Note 2: When an instruction that clears the GIE bit
less of the status of their corresponding
mask bit or the GIE bit.
is executed, any interrupts that were
pending for execution in the next cycle are
ignored. The CPU will execute a NOP in
the cycle immediately following the
instruction which clears the GIE bit. The
interrupts which were ignored are still
pending to be serviced when the GIE bit is
set again.
GIE
1996 Microchip Technology Inc.
Wake-up
(If in SLEEP mode)
Interrupt
to CPU