PIC16C642-04/SO Microchip Technology, PIC16C642-04/SO Datasheet - Page 67

• Manufacturer Part Number: PIC16C642-04/SO
• Description: IC MCU OTP 4KX14 COMP 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C642-04/SO

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, WDT
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 22
• Ram Memory Size: 176Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 176 B
• Interface Type: RS- 232
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

9.5.1
The external interrupt on the RB0/INT pin is edge trig-
gered: either rising if bit INTEDG (OPTION<6>) is set,
or falling, if bit INTEDG is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be enabled/dis-
abled
(INTCON<4>). The INTF bit must be cleared in soft-
ware in the interrupt service routine before re-enabling
this interrupt. The RB0/INT interrupt can wake-up the
processor from SLEEP, if bit INTE was set prior to
going into SLEEP. The status of the GIE bit decides
whether or not the processor branches to the interrupt
vector following wake-up. See Section 9.8 for details
on SLEEP and Figure 9-19 for timing of wake-up from
SLEEP through RB0/INT interrupt.
9.5.2
An overflow (FFh
set the T0IF (INTCON<2>) bit. The interrupt can
be
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0.
FIGURE 9-16: RB0/INT PIN INTERRUPT TIMING
1996 Microchip Technology Inc.
INSTRUCTION FLOW
Note 1: INTF flag is sampled here (every Q1).
GIE bit
(INTCON<7>)
INTF flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Instruction
executed
Instruction
fetched
PC
enabled/disabled
2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
by
RB0/INT INTERRUPT
TMR0 INTERRUPT
on
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3
setting/clearing
the
Q1
Inst (PC-1)
RB0/INT
Inst (PC)
00h) in the TMR0 register will
1
Q2
PC
by
Q3
4
setting/clearing
pin,
Q4
enable
5
Q1
flag
Inst (PC+1)
Inst (PC)
Q2
bit
1
bit
PC+1
Q3
INTE
INTF
T0IE
Preliminary
PIC16C64X & PIC16C66X
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
9.5.3
An input change on any bit of PORTB<7:4> sets flag bit
RBIF (INTCON<0>). The interrupt can be enabled/dis-
abled
(INTCON<4>). For operation of PORTB (Section 5.2).
9.5.4
See Section 7.6 for complete description of the com-
parator interrupt.
PC+1
—
Q3
by
Q4
PORTB INTERRUPT
COMPARATOR INTERRUPT
2
Q1
setting/clearing
Dummy Cycle
Inst (0004h)
Q2
0004h
Q3
Q4
enable
Q1
DS30559A-page 67
Inst (0005h)
Q2
Inst (0004h)
0005h
bit
Q3
Q4
RBIE