ATMEGA3250PV-10AUR Atmel, ATMEGA3250PV-10AUR Datasheet - Page 16
ATMEGA3250PV-10AUR
Manufacturer Part Number
ATMEGA3250PV-10AUR
Description
MCU AVR 32K FLASH 10MHZ 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA3250P-20AU.pdf
(364 pages)
Specifications of ATMEGA3250PV-10AUR
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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6.6.1
6.7
16
Instruction Execution Timing
ATmega325P/3250P
SPH and SPL – Stack Pointer High and Stack Pointer Low
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 1
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 1. The Parallel Instruction Fetches and Instruction Executions
Figure 2
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 2. Single Cycle ALU Operation
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
shows the parallel instruction fetches and instruction executions enabled by the Har-
shows the internal timing concept for the Register File. In a single clock cycle an ALU
Result Write Back
SP15
SP7
R/W
R/W
15
7
0
0
clk
clk
CPU
CPU
SP14
SP6
R/W
R/W
14
6
0
0
SP13
R/W
R/W
SP5
CPU
13
5
0
0
T1
T1
, directly generated from the selected clock source for the
SP12
SP4
R/W
R/W
12
4
0
0
SP11
T2
R/W
R/W
SP3
T2
11
3
0
0
SP10
SP2
R/W
R/W
10
2
0
0
T3
T3
R/W
SP9
SP1
R/W
9
1
0
0
SP8
SP0
R/W
R/W
8
0
0
0
8023F–AVR–07/09
T4
T4
SPH
SPL
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