ATMEGA3250PV-10AUR Atmel, ATMEGA3250PV-10AUR Datasheet - Page 56

• Manufacturer Part Number: ATMEGA3250PV-10AUR
• Description: MCU AVR 32K FLASH 10MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3250PV-10AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.2.1
11.3
11.3.1
56
Register Description
ATmega325P/3250P
Moving Interrupts Between Application and Boot Space
MCUCR – MCU Control Register
The MCU Control Register controls the placement of the Interrupt Vector table.
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-
mined by the BOOTSZ Fuses. Refer to the section
Self-Programming” on page 256
tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note:
Bit
0x35 (0x55)
Read/Write
Initial Value
Address Labels Code
;
.org 0x3800/0x7800
0x3800/0x7800
0x3802/0x7802
0x3804/0x7804
...
0x382C/0x782C
;
0x382E/0x782ERESET:ldir16,high(RAMEND); Main program start
0x382F/0x782F
0x3830/0x7830
0x3831/0x7831
0x3832/0x7832
0x3833/0x7833
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section
Write Self-Programming” on page 256
R/W
JTD
7
0
jmp
jmp
jmp
...
jmp
out
ldi
out
sei
<instr>
BODS
R
6
0
RESET
EXT_INT0
PCINT0
...
SPM_RDY
SPH,r16
r16,low(RAMEND)
SPL,r16
xxx
BODSE
for details. To avoid unintentional changes of Interrupt Vector
R
5
0
; Store Program Memory Ready Handler
for details on Boot Lock bits.
PUD
R/W
4
0
; Set Stack Pointer to top of RAM
Comments
; Reset handler
; IRQ0 Handler
; PCINT0 Handler
;
; Enable interrupts
”Boot Loader Support – Read-While-Write
R
3
–
0
”Boot Loader Support – Read-While-
R
2
–
0
IVSEL
R/W
1
0
IVCE
R/W
0
0
8023F–AVR–07/09
MCUCR