PIC18F4510-E/ML Microchip Technology, PIC18F4510-E/ML Datasheet - Page 2
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PIC18F4510-E/ML
Manufacturer Part Number
PIC18F4510-E/ML
Description
IC MCU FLASH 16KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18LF2410-ISO.pdf
(376 pages)
4.PIC18LF2410-ISO.pdf
(8 pages)
5.PIC18LF2410-ISO.pdf
(16 pages)
6.PIC18LF2410-ISO.pdf
(6 pages)
7.PIC18LF2410-ISO.pdf
(6 pages)
8.PIC18LF2410-ISO.pdf
(8 pages)
Specifications of PIC18F4510-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
For Use With
I3DB18F4620 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
PIC18F2410/2510/4410/4510
2. Module: MSSP
3. Module: MSSP
DS80277C-page 2
After an I
register may be written for up to 10 T
additional writes are blocked. The data transfer may
be corrupted if SSPBUF is written during this time.
The WCOL bit is set any time an SSPBUF write
occurs during a transfer.
Work around
Avoid writing SSPBUF until the data transfer is
complete, indicated by the setting of the SSPIF bit
(PIR1<3>).
Verify the WCOL bit (SSPCON1<7>) is clear after
writing SSPBUF to ensure any potential transfer in
progress is not corrupted.
Date Codes that pertain to this issue:
All engineering and production devices.
In 10-Bit Addressing mode, when a Repeated Start
is issued followed by the high address byte and a
write command (R/W = 0), an ACK is not issued.
Work around
There are two work arounds available:
1. Single Master Environment:
In a single master environment, the user must
issue a Stop, then a Start followed by a write to the
address high, then the address low followed by the
data.
2. Multi-Master Environment:
In a multi-master environment, the user must issue
a Repeated Start, send a dummy write command
to a different address, issue another Repeated
Start and then send a write to the original address.
This procedure will help maintain control of the
bus.
Date Codes that pertain to this issue:
All engineering and production devices.
2
C transfer is initiated, the SSPBUF
CY
before
4. Module: MSSP
5. Module: ECCP
I
bit should be set) only when the system is idle
(i.e., when ACKEN, RCEN, PEN, RSEN and SEN
all equal zero). It should not be possible to set the
RCEN bit when the system is not idle, however,
the RCEN bit can be set under this circumstance.
Work around
Wait for the system to become idle before setting the
RCEN bit. This requires a check for the following bits
to be clear:
ACKEN, RCEN, PEN, RSEN and SEN.
Date Codes that pertain to this issue:
All engineering and production devices.
When the CCP1 auto-shutdown feature is
configured for automatic restart by setting the
PRSEN bit (PWM1CON<7>), the pulse terminates
immediately in a shutdown event. In addition, the
pulse may restart within the period if the shutdown
condition expires. This may result in the generation
of short pulses on the PWM output(s).
Work around
Configure the auto-shutdown for software restart
by clearing the PRSEN bit (PWM1CON<7>). The
PWM can be re-enabled by clearing the
ECCPASE bit (ECCP1AS<7>) after the shutdown
condition expires.
Date Codes that pertain to this issue:
All engineering and production devices.
2
C Receive mode should be enabled (i.e., RCEN
© 2007 Microchip Technology Inc.