PIC18F4510-E/ML Microchip Technology, PIC18F4510-E/ML Datasheet - Page 3
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PIC18F4510-E/ML
Manufacturer Part Number
PIC18F4510-E/ML
Description
IC MCU FLASH 16KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18LF2410-ISO.pdf
(376 pages)
4.PIC18LF2410-ISO.pdf
(8 pages)
5.PIC18LF2410-ISO.pdf
(16 pages)
6.PIC18LF2410-ISO.pdf
(6 pages)
7.PIC18LF2410-ISO.pdf
(6 pages)
8.PIC18LF2410-ISO.pdf
(8 pages)
Specifications of PIC18F4510-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
For Use With
I3DB18F4620 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
6. Module: ECCP
EXAMPLE 1:
7. Module: ECCP
© 2007 Microchip Technology Inc.
When monitoring a shutdown condition using a bit
test on the ECCPASE bit (ECCP1AS<7>), or
performing a bit operation on the ECCPASE bit,
the device may produce unexpected results.
Work around
Before performing a bit test or bit operation on the
ECCPASE bit, copy the ECCP1AS register to the
working register and perform the operation there.
By avoiding these operations on the ECCPASE bit
in the ECCP1AS register, the module will operate
normally.
In Example 1, ECCPASE bit operations are
performed on the W register.
Date Codes that pertain to this issue:
All engineering and production devices.
The auto-shutdown source, FLT0, has inverse
polarity from the description in Section 15.4.7
“Enhanced PWM Auto-Shutdown” of the Device
Data Sheet. A logic high-voltage level on FLT0 will
generate a shutdown on CCP1.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
MOVF
BTFSC
BRA
ECCP1AS, W
WREG, ECCPASE
SHUTDOWN_ROUTINE
PIC18F2410/2510/4410/4510
8. Module: ECCP and CCP
9. Module: ECCP
The CCP1 and CCP2 configured for PWM mode,
with 1:1 Timer2 prescaler and duty cycle set to the
period minus 1, may result in the PWM output(s)
remaining at a logic low level.
Clearing the PR2 register to select the fastest
period may also result in the output(s) remaining at
a logic low output level.
Work around
To ensure a reliable waveform, verify that the
selected duty cycle does not equal the 10-bit
period minus 1 prior to writing these locations, or
use 1:4 or 1:16 Timer2 prescale. Also, verify the
PR2 register is not written to 00h.
All other duty cycle and period settings will function
as described in the Device Data Sheet.
The ECCP and CCP modules remain capable of
10-bit accuracy.
Date Codes that pertain to this issue:
All engineering and production devices.
CCP1
Comparator 1 corrupts the PWM duty cycle pulse.
In addition, it does not always synchronize the
pulse to the beginning of the period and the end of
the pulse can occur at any time within the period.
Work around
Use
Applications which can tolerate a shutdown
response time of several T
parator interrupt flag to detect a shutdown event
and disable the PWM by clearing the ECCPASE
bit (ECCP1AS<7>).
Date Codes that pertain to this issue:
All engineering and production devices.
FLT0
configured
for
the
for
auto-shutdown
CY
auto-shutdown
s may use the com-
DS80277C-page 3
source.
with