AT32UC3B164-AUT Atmel, AT32UC3B164-AUT Datasheet - Page 525
![IC MCU AVR32 64KB FLASH 48-TQFP](/photos/6/82/68248/313-48-vqfp_sml.jpg)
AT32UC3B164-AUT
Manufacturer Part Number
AT32UC3B164-AUT
Description
IC MCU AVR32 64KB FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B164-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
28
Ram Memory Size
16KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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24.6.2
24.6.2.1
Figure 24-3. Functional View of the Channel Block Diagram
24.6.2.2
32059I–06/2010
PWM Channel
Block Diagram
inputs from
Waveform Properties
from clock
Peripheral
generator
inputs
Bus
Channel
The clock generator is divided in three blocks:
Each linear divider can independently divide one of the clocks of the modulo n counter. The
selection of the clock to be divided is made according to the PREA (PREB) field of the PWM
Mode register (MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB)
field value in the PWM Mode register (MR).
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register
are set to 0. This implies that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situa-
tion is also true when the PWM master clock is turned off through the Power Management
Controller.
Each of the 7 channels is composed of three blocks:
• A clock selector which selects one of the clocks provided by the clock generator described in
• An internal counter clocked by the output of the clock selector. This internal counter is
• A comparator used to generate events according to the internal counter value. It also computes
The different properties of output waveforms are:
• the internal clock selection. The internal channel counter is clocked by one of the clocks
• the waveform period. This channel parameter is defined in the CPRD field of the CPRDx
Selector
Clock
Section 24.6.1 ”PWM Clock Generator” on page
incremented or decremented according to the channel configuration and comparators events.
The size of the internal counter is 20 bits.
the PWMx output waveform according to the configuration.
provided by the clock generator described in the previous section. This channel parameter is
defined in the CPRE field of the CMRx register. This field is reset at 0.
register.
– a modulo n counter which provides 11 clocks: F
– two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and
F
clkB
MCK
/32, F
MCK
/64, F
Counter
Internal
MCK
/128, F
MCK
/256, F
Comparator
MCK
524.
/512, F
MCK
, F
MCK
MCK
/1024
/2, F
MCK
PWMx output waveform
/4, F
AT32UC3B
MCK
/8, F
MCK
/16,
525
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