AT32UC3B164-AUT Atmel, AT32UC3B164-AUT Datasheet - Page 596

• Manufacturer Part Number: AT32UC3B164-AUT
• Description: IC MCU AVR32 64KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B164-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Controller Family/series: AT32UC3B
• No. Of I/o's: 28
• Ram Memory Size: 16KB
• Cpu Speed: 60MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

27.4.11.1
27.4.11.2
27.4.11.3
27.4.11.4
32059I–06/2010
SAB Address Mode
Block Transfer
Canceling a SAB Access
Busy Reporting
which is linked to the JTAG through a bus master module, which also handles synchronization
between the TCK and SAB clocks.
For more information about the SAB and a list of SAB slaves see the Service Access Bus
chapter.
The MEMORY_SIZED_ACCESS instruction allows a sized read or write to any 36-bit address
on the bus. MEMORY_WORD_ACCESS is a shorthand instruction for 32-bit accesses to any
36-bit address, while the NEXUS_ACCESS instruction is a Nexus-compliant shorthand instruc-
tion for accessing the 32-bit OCD registers in the 7-bit address space reserved for these. These
instructions require two passes through the Shift-DR TAP state: one for the address and control
information, and one for data.
To increase the transfer rate, consecutive memory accesses can be accomplished by the
MEMORY_BLOCK_ACCESS instruction, which only requires a single pass through Shift-DR for
data transfer only. The address is automatically incremented according to the size of the last
SAB transfer.
It is possible to abort an ongoing SAB access by the CANCEL_ACCESS instruction, to avoid
hanging the bus due to an extremely slow slave.
As the time taken to perform an access may vary depending on system activity and current chip
frequency, all the SAB access JTAG instructions can return a busy indicator. This indicates
whether a delay needs to be inserted, or an operation needs to be repeated in order to be suc-
cessful. If a new access is requested while the SAB is busy, the request is ignored.
The SAB becomes busy when:
• Entering Update-DR in the address phase of any read operation, e.g., after scanning in a
• Entering Update-DR in the data phase of any write operation, e.g., after scanning in data for a
• Entering Update-DR during a MEMORY_BLOCK_ACCESS.
• Entering Update-DR after scanning in a counter value for SYNC.
• Entering Update-IR after scanning in a MEMORY_BLOCK_ACCESS if the previous access
The SAB becomes ready again when:
• A read or write operation completes.
• A SYNC countdown completed.
• A operation is cancelled by the CANCEL_ACCESS instruction.
What to do if the busy bit is set:
• During Shift-IR: The new instruction is selected, but the previous operation has not yet
NEXUS_ACCESS address with the read bit set.
NEXUS_ACCESS write.
was a read and data was scanned after scanning the address.
completed and will continue (unless the new instruction is CANCEL_ACCESS). You may
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