AT32UC3B164-AUT Atmel, AT32UC3B164-AUT Datasheet - Page 654

• Manufacturer Part Number: AT32UC3B164-AUT
• Description: IC MCU AVR32 64KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B164-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Controller Family/series: AT32UC3B
• No. Of I/o's: 28
• Ram Memory Size: 16KB
• Cpu Speed: 60MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

31.2.1.5
31.2.1.6
31.2.1.7
32059I–06/2010
USB
ADC
PDCA
2. Additional delay on TD output
3. TF output is not correct
1. For isochronous pipe, the INTFRQ is irrelevant
1. Sleep Mode activation needs additional A to D conversion
1. Wrong PDCA behavior when using two PDCA channels with the same PID
2. Transfer error will stall a transmit peripheral handshake interface
The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when:
Clock is CKDIV
The START is selected on either a frame synchro edge or a level,
Frame synchro data is enabled,
Transmit clock is gated on output (through CKO field).
Fix/Workaround
Transmit or receive CLOCK must not be gated (by the mean of CKO field) whenSTART con-
dition is performed on a generated frame synchro.
A delay from 2 to 3 system clock cycles is added to TD output when:
TCMR.START = Receive Start,
TCMR.STTDLY = more than ZERO,
RCMR.START = Start on falling edge / Start on Rising edge / Start on any edge,
RFMR.FSOS = None (input).
Fix/Workaround
None.
TF output is not correct (at least emitted one serial clock cycle later than expected) when:
TFMR.FSOS = Driven Low during data transfer/ Driven High during data transfer
TCMR.START = Receive start
RFMR.FSOS = None (Input)
RCMR.START = any on RF (edge/level)
Fix/Workaround
None.
IN and OUT tokens are sent every 1 ms (Full Speed).
Fix/Workaround
For longer polling time, the software must freeze the pipe for the desired period in order to
prevent any "extra" token.
If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
Wrong PDCA behavior when using two PDCA channels with the same PID.
Fix/Workaround
The same PID should not be assigned to more than one channel.
If a tranfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
Fix/workaround:
AT32UC3B
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