ATMEGA645P-MU Atmel, ATMEGA645P-MU Datasheet - Page 270
![IC MCU AVR 64K FLASH 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA645P-MU
Manufacturer Part Number
ATMEGA645P-MU
Description
IC MCU AVR 64K FLASH 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA645P-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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25.5
270
Boot Loader Lock Bits
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645
If no Boot Loader capability is needed, the entire Flash is available for application code. The
Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives
the user a unique flexibility to select different levels of protection.
The user can select:
• To protect the entire Flash from a software update by the MCU.
• To protect only the Boot Loader Flash section from a software update by the MCU.
• To protect only the Application Flash section from a software update by the MCU.
• Allow software update in the entire Flash.
See
and general Lock bits can be set in software and in Serial or Parallel Programming mode, but
they can be cleared by a Chip Erase command only. The general Write Lock (Lock Bit mode 2)
does not control the programming of the Flash memory by SPM instruction. Similarly, the gen-
eral Read/Write Lock (Lock Bit mode 1) does not control reading nor writing by LPM/SPM, if it is
attempted.
Table 25-2.
Note:
Table 25-3.
Note:
BLB1 Mode
BLB0 Mode
Table 25-2 on page 270
1
2
3
4
1
2
3
4
1. “1” means unprogrammed, “0” means programmed
1. “1” means unprogrammed, “0” means programmed
Boot Lock Bit0 Protection Modes (Application Section)
Boot Lock Bit1 Protection Modes (Boot Loader Section)
BLB12
BLB02
1
1
0
0
1
1
0
0
BLB11
BLB01
and
1
0
0
1
1
0
0
1
Table 25-3 on page 270
Protection
No restrictions for SPM or LPM accessing the Boot Loader
section.
SPM is not allowed to write to the Boot Loader section.
SPM is not allowed to write to the Boot Loader section, and LPM
executing from the Application section is not allowed to read
from the Boot Loader section. If Interrupt Vectors are placed in
the Application section, interrupts are disabled while executing
from the Boot Loader section.
LPM executing from the Application section is not allowed to
read from the Boot Loader section. If Interrupt Vectors are
placed in the Application section, interrupts are disabled while
executing from the Boot Loader section.
Protection
No restrictions for SPM or LPM accessing the Application
section.
SPM is not allowed to write to the Application section.
SPM is not allowed to write to the Application section, and LPM
executing from the Boot Loader section is not allowed to read
from the Application section. If Interrupt Vectors are placed in
the Boot Loader section, interrupts are disabled while executing
from the Application section.
LPM executing from the Boot Loader section is not allowed to
read from the Application section. If Interrupt Vectors are placed
in the Boot Loader section, interrupts are disabled while
executing from the Application section.
for further details. The Boot Lock bits
(1)
(1)
8285B–AVR–03/11
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